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Feb 1, 2023 at 22:41 comment added occipita As an aside, commodity chips are now available with 56-bit physical address support, e.g. Intel's Xeon "Ice Lake" server chips, although AFAICT the current implementation doesn't support any more memory than previously due to the limitations of how much memory you can attach per DDR5 channel.
Sep 8, 2020 at 15:04 comment added peterh @TooTea Wow, it is more sophisticated as I've tought.
Sep 8, 2020 at 14:38 comment added TooTea @peterh-ReinstateMonica Well, of course only a part of the RAM modules is physically connected to the pins of the integrated memory controller in any single CPU. However, all CPUs can access all of the memory through the interconnect (QPI and NUMAlink). It works exactly the same as any ordinary dual socket server.
Sep 8, 2020 at 14:23 comment added peterh @TooTea Thanks, but I think the CPUs see here different address spaces. If I guess well, a single CPU can see only a part of the whole memory, making its address pins partially unused.
Sep 8, 2020 at 14:19 comment added TooTea @peterh-ReinstateMonica Big shared memory machines like the SGI (now HPE) UltraViolet series are routinely sold with a dozen TBs of RAM or so (IIRC supporting up to 64 TB RAM). I guess they just aren't commonly sold on eBay.
Sep 8, 2020 at 8:47 comment added peterh Afaik even this 48-bit is only for hardware io mappings, on the ebay I could find servers with 1TB RAM at most (price about $50000).
Sep 8, 2020 at 8:41 comment added peterh Side note: the CPU actually had 20 address lines, i.e. externally (from the view of the motherboard), yes it was a CPU with 20-bit adresses. The segmentation was used only internally, i.e. there were no "20-bit pointers", instead 32-bit "pointers" were used, and converted on the fly to 20-bit addresses as you write.
Sep 8, 2020 at 7:01 review First posts
Sep 8, 2020 at 8:47
Sep 8, 2020 at 6:59 history answered NotJohnDoe CC BY-SA 4.0