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Brian H
Brian H
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When the C128 is running in its native mode, the only "fixed" memory addresses are $FF00-$FF04. These 5 bytes allow access to the first 5 registers of the MMU regardless of the current memory configuration (which is controlled via the MMU).

The MMU's RAM Configuration Register, which is in I/O space at $D500, but always available at $FF00, controls how ROM, RAM, and I/O are banked in and out of the memory map. Using this register, you can certainly bank the Kernal ROM out, and thus allow access to interrupt vectors stored in RAM.

You may have been considering the other ability of the MMU to allow common areas of RAM that are in Bank 0 but also seen when accessing Bank 1. These optional shared RAM areas can occur at the bottom and at the top of RAM in various configurations. The top RAM sharing does share $FF00-$FFFF between the two RAM banks. But this is independent of the RAM or ROM being visible in that region of the memory map (as described above).

You can test all of this in BASIC right after cold starting.

BANK 15:PRINT PEEK(65534) - this prints "23"
BANK 0:POKE 65534, 18
PRINT PEEK(65534)         - this prints "18"
BANK 15:PRINT PEEK(65534) - back to "23"

When the C128 is running in its native mode, the only "fixed" memory addresses are $FF00-$FF04. These 5 bytes allow access to the first 5 registers of the MMU regardless of the current memory configuration (which is controlled via the MMU).

The MMU's RAM Configuration Register, which is in I/O space at $D500, but always available at $FF00, controls how ROM, RAM, and I/O are banked in and out of the memory map. Using this register, you can certainly bank the Kernal ROM out, and thus allow access to interrupt vectors stored in RAM.

You may have been considering the other ability of the MMU to allow common areas of RAM that are in Bank 0 but also seen when accessing Bank 1. These optional shared RAM areas can occur at the bottom and at the top of RAM in various configurations. The top RAM sharing does share $FF00-$FFFF between the two RAM banks. But this is independent of the RAM or ROM being visible in that region of the memory map (as described above).

When the C128 is running in its native mode, the only "fixed" memory addresses are $FF00-$FF04. These 5 bytes allow access to the first 5 registers of the MMU regardless of the current memory configuration (which is controlled via the MMU).

The MMU's RAM Configuration Register, which is in I/O space at $D500, but always available at $FF00, controls how ROM, RAM, and I/O are banked in and out of the memory map. Using this register, you can certainly bank the Kernal ROM out, and thus allow access to interrupt vectors stored in RAM.

You may have been considering the other ability of the MMU to allow common areas of RAM that are in Bank 0 but also seen when accessing Bank 1. These optional shared RAM areas can occur at the bottom and at the top of RAM in various configurations. The top RAM sharing does share $FF00-$FFFF between the two RAM banks. But this is independent of the RAM or ROM being visible in that region of the memory map (as described above).

You can test all of this in BASIC right after cold starting.

BANK 15:PRINT PEEK(65534) - this prints "23"
BANK 0:POKE 65534, 18
PRINT PEEK(65534)         - this prints "18"
BANK 15:PRINT PEEK(65534) - back to "23"
Source Link
Brian H
Brian H
  • 61.5k
  • 20
  • 207
  • 366

When the C128 is running in its native mode, the only "fixed" memory addresses are $FF00-$FF04. These 5 bytes allow access to the first 5 registers of the MMU regardless of the current memory configuration (which is controlled via the MMU).

The MMU's RAM Configuration Register, which is in I/O space at $D500, but always available at $FF00, controls how ROM, RAM, and I/O are banked in and out of the memory map. Using this register, you can certainly bank the Kernal ROM out, and thus allow access to interrupt vectors stored in RAM.

You may have been considering the other ability of the MMU to allow common areas of RAM that are in Bank 0 but also seen when accessing Bank 1. These optional shared RAM areas can occur at the bottom and at the top of RAM in various configurations. The top RAM sharing does share $FF00-$FFFF between the two RAM banks. But this is independent of the RAM or ROM being visible in that region of the memory map (as described above).