Timeline for z80 crashes after executing some instructions
Current License: CC BY-SA 3.0
11 events
when toggle format | what | by | license | comment | |
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Dec 11, 2017 at 20:04 | comment | added | C32 | oh man my comment earlier was stupid. just connect rom's cs to mreq | |
Dec 11, 2017 at 18:27 | comment | added | Tommy | Open collector probably implies the logical AND if two devices output at once? I'm no expert, apply a pinch of salt to that guess. | |
Dec 11, 2017 at 17:36 | comment | added | user3570736 | Ah, yeah. The Z80 puts A on the top half of the address bus in the OUT (00),A instruction. As soon as A wraps round to 0 this was pulling A15 low. The Z80 and ROM would then both be trying to write to the data bus at the same time, and I don't know what that would do but it probably wouldn't be good! | |
Dec 11, 2017 at 15:30 | vote | accept | C32 | ||
Dec 12, 2017 at 12:05 | |||||
Dec 11, 2017 at 15:28 | vote | accept | C32 | ||
Dec 11, 2017 at 15:30 | |||||
Dec 11, 2017 at 15:18 | vote | accept | C32 | ||
Dec 11, 2017 at 15:27 | |||||
Dec 11, 2017 at 15:17 | vote | accept | C32 | ||
Dec 11, 2017 at 15:18 | |||||
Dec 11, 2017 at 15:14 | comment | added | C32 | IT WORKS!!!! \o/ i put an or gate on /rfsh and /rd and then going to the chip select of my rom instead of just putting cs to A15 and it worked!!!!! i believe now i should or that with a15 too , to add a ram. | |
Dec 11, 2017 at 15:10 | comment | added | Tommy | Except that, as per a precious commenter, doesn't the Z80's refresh counter count in its low seven bits only? Bit 7 is always whatever you loaded R with. | |
Dec 11, 2017 at 9:42 | history | edited | tofro | CC BY-SA 3.0 |
added 145 characters in body
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Dec 11, 2017 at 9:20 | history | answered | tofro | CC BY-SA 3.0 |