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Maybe to start with the obvious: Not every device needs to be interrupt driven.

Maybe to start with the obvious:

• Not every device needs to be interrupt driven.
• Most devices will occupy more than a single I/O address.

Or, instead of an RST, a CALL can be delivered (*2). When the 8080 (or Z80 in Mode 0) senses a CALL opcode during an interrupt cycle it will issue two more ccles to fetch an address to be used. Thus there can be as many different entrypoints as one wishes (*3)

Or, instead of an RST, a CALL can be delivered (*2). When the 8080 (or Z80 in Mode 0) senses a CALL opcode during an interrupt cycle it will issue two additional cycles to fetch the address to be used. Thus there can be as many different entrypoints as one wishes (*3)

An interrupt controller (like 8259) can issue one RST for all interrupts, having them all initiate the same routine and then be polled by the routine to check which is the one to be served. Or they can have separate. Or a mixture of both. It's up to the systems requirements (and what style the designer preferred).

Or, instead of an RST, a CALL can be delivered. When the 8080 (or Z80 in Mode 0) senses a CALL opcode during an interrupt cycle it will issue two more ccles to fetch an address to be used. Thus there can be as many different entrypoints as one wishes (*1)

No. The S100 bus (in actual use, not as with the original Altair) supports three interrupt lines: /RESET, /NMI and /INT which connect all slots in parallel. Ignoring /RESET and /NMI, there is only one line, thus there can not be a slot specific assignment (*2). It all depends on the CPU used, the interrupt mode used and programming of the interrupt controller used.

But as there is only one interrupt, it is the same for all devices. The routine is selected by what instruction is placed on the bus during an interrupt cycle by the interrupt controller. In case of an 8080/85, it will be one of 8 possible RST instructions inserted by the 8259 interrupt controller as well an arbitary CALL instruction. In case of a Z80 (Interrupt Mode 3) it might also be one of 128 vector numbers.

*1 - Within the reasoning of a system with only 64 KiB address space of course :))

*2 - Keep in mind, S100 is a simple parallel bus utilizing an undefined number of slots. None is prioritized or special in any way. Any card can be placed in any slot. Much like the PC bus system. In contrast the Apple II bus uses geographical addressing, meaning while each slot is electrical the same (lets ignore #0 and #7 for this), they will be seen on different address ranges by the CPU. That would be geographical addressing - which S100 is not.

An interrupt controller (like 8259 *1) can issue one RST for all interrupts, having them all initiate the same routine and then be polled by the routine to check which is the one to be served. Or they can have separate. Or a mixture of both. It's up to the systems requirements (and what style the designer preferred).

Or, instead of an RST, a CALL can be delivered (*2). When the 8080 (or Z80 in Mode 0) senses a CALL opcode during an interrupt cycle it will issue two more ccles to fetch an address to be used. Thus there can be as many different entrypoints as one wishes (*3)

No. The S100 bus (in actual use, not as with the original Altair) supports three interrupt lines: /RESET, /NMI and /INT which connect all slots in parallel. Ignoring /RESET and /NMI, there is only one line, thus there can not be a slot specific assignment (*4). It all depends on the CPU used, the interrupt mode used and programming of the interrupt controller used.

But as there is only one interrupt, it is the same for all devices. The routine is selected by what instruction is placed on the bus during an interrupt cycle by the interrupt controller. In case of an 8080/85, it will be one of 8 possible RST instructions inserted by the 8259 interrupt controller as well an arbitary CALL instruction. In case of a Z80 (Interrupt Mode 3) it might also be one of 128 vector numbers.

Now, if your question is about the 8 seperate interrupt lines usually called VI0..VI7, then again, they are shared between all boards and it's up to the system configuration if they get assigned to seperate boards (usually by jumpers) or get used by multiple - in both cases again, they can be used by one or more devices on these boards. Wellcome to the wonderful world of S100 bus configuration :))

Remember there is only one interrupt line on the CPU, so handling 8 lines from the bus means, that there must be an interrupt controller (8259) on the CPU board to encode and prioritize them. Otherwise they might be a bit hard to handle.

Confused? Well, interrupt handling isn't the easyest lesson to learn when about a CPU, especially not with rather sophisticated mechanics like on the 8080/Z80 family. Just take your time an gnaw thru all the paper :)

*1 - Usually the 8259 is associated with vectored interrupts (RST or CALL). There are other chips, like the 8214, but they lack the ability to issue different vectors (or vectors at all).

*2 - IIRC, any instruction can be issued, but only RST and CALL do make sense under normal circumstances as they both do a proper subroutine invocation. Then again, with a careful design other instructions could be useful in the right situation.

*3 - Within the reasoning of a system with only 64 KiB address space of course :))

*4 - Keep in mind, S100 is a simple parallel bus utilizing an undefined number of slots. None is prioritized or special in any way. Any card can be placed in any slot. Much like the PC bus system. In contrast the Apple II bus uses geographical addressing, meaning while each slot is electrical the same (lets ignore #0 and #7 for this), they will be seen on different address ranges by the CPU. That would be geographical addressing - which S100 is not.