How did the Apple IIGS automatically slow 5.25 inch disk I/O code for backwards compatability?

Question

Apple II software often used hard-coded timing for 5.25 inch floppy disk I/O, for example to control the duration of each track step or the rate at which bytes are written and read from the disk. Since the Apple IIGS had a faster 2.8 MHz CPU than earlier 1 MHz Apple II models, code that performed disk I/O needed to be slowed to 1 MHz execution speed in order to work as expected. How was this done?

I think I know part of the answer: the first sector on a 5.25 inch floppy disk is loaded into RAM using a small ROM routine located at $C600. This is the IIGS's built-in equivalent of the Disk II Controller Card. As I understand it, the CPU is automatically slowed to 1 MHz when executing code from this memory range. And the CPU is also slowed to 1 MHz when accessing memory-mapped I/O locations used by the disk controller hardware.

But after sector zero is loaded into RAM, most disks would begin a bootstrap process in which additional code for handling disk I/O was loaded to RAM and executed directly from RAM. For DOS this would be RWTS; for other disks it might be something custom. How did the IIGS know to also run this code at the slower 1 MHz speed?

I've been using a logic analyzer to examine the disk I/O activity while booting a DOS 3.3 System Master and a few other 5.25 inch floppy disks on a IIGS. I've examined the lengths of the pulses on the PHASE inputs when stepping between tracks, as an indicator of the speed at which the disk I/O code is running. Using the IIGS built-in disk controller, the pulse lengths are the same whether the CPU is set to fast (2.8 MHz) or normal (1 MHz) speeds, and disks loads normally at either speed. But with the custom disk controller card that I'm developing, after sector zero gets loaded, the pulse lengths are about 2.5x shorter when the CPU speed is set to fast, and most disks don't boot properly. It seems that I've inadvertently broken whatever mechanism the IIGS normally uses to keep disk I/O code running at backwards-compatible 1 MHz speeds. How is that handled normally?

Answer 1

From the Apple IIgs Hardware Reference, Second Edition, pages 22-24:

Figure 2-6 - Speed register at SC036

Table 2-2 - Bits set in the Speed register

[...]

Bits 0-3†

Value 1

Description Disk II motor-on address detectors: To retain Apple II peripheral compatibility, the motor-on detectors change the system speed to 1.024 MHz whenever a Disk II motor-on address is detected.‡ When the disk motor-off address is accessed, the system speed increases, to 2.8 MHz again. For example, when bit 1 is 1, the FPI switches to 1.024 MHz when address $C0D9 is accessed, and returns to 2.8 MHz following a $C0D8 access. (See list of addresses below.)

Value 0

When this bit is 0, the Disk II motor detectors are turned off.

Bits 0 through 3 detect the following addresses:

Bit  Slot  Motor on  Motor off
0    4     $C0C9     $C0C8
1    5     $C0D9     $C0D8
2    6     $C0E9     $C0E8
3    7     $C0F9     $C0F8

* Drives designed for the Apple IIGS system should use the speed bit (Speed register bit 7) to change the processor speed when accessing disks, rather than the disk motor-on detectors (speed register bits 0 through 3). By using bit 7 you access drives in slots other than 4 through 7 by changing the system speed manually. Be aware that central processor speed changes for drive compatibility may affect application program timing; avoid using the motor addresses unless they are used in a fashion consistent with the drive's central processor speed requirements.

† For compatibility with future Apple products, use firmware calls only to manipulate bits 0 to 3 of the Speed register.

‡ Drives designed for previous Apple II computers will function as Apple IIGS peripherals only if the system speed is changed to 1.024 MHz before disk access is attempted.

Luckily we can use MAME to see how it's set by running it with a Disk II card:

mame apple2gsr1 -sl6 diskiing -debug

Then setting watch points for $C600-$C6FF and $C036:

wp c600,100,rw
wp c036,1,rw

Here's the output.

MAME debugger version 0.229 (mame0229)
Currently targeting apple2gsr1 (Apple IIgs (ROM01))
>wp c600,100,rw
Watchpoint 1 set
>wp c036,1,rw
Watchpoint 2 set
Stopped at watchpoint 2 reading 80 from 0000C036 (PC=F8A6)
Stopped at watchpoint 2 writing 80 to 0000C036 (PC=F8AC)
Stopped at watchpoint 1 reading 03 from 0000C605 (PC=FFFA07)
Stopped at watchpoint 1 reading 00 from 0000C603 (PC=FFFA07)
Stopped at watchpoint 1 reading 20 from 0000C601 (PC=FFFA07)
Stopped at watchpoint 1 reading 00 from 0000C6FF (PC=FFFA12)
Stopped at watchpoint 2 writing 84 to 0000C036 (PC=FFFFE2)
Stopped at watchpoint 2 writing 80 to 0000C036 (PC=F8B4)
...
Stopped at watchpoint 2 reading 80 from 0000C036 (PC=F8A6)
Stopped at watchpoint 2 writing 80 to 0000C036 (PC=F8AC)
Stopped at watchpoint 1 reading 00 from 0000C6FB (PC=FFA268)
Stopped at watchpoint 2 reading 80 from 0000C036 (PC=FF7082)
Stopped at watchpoint 2 writing 80 to 0000C036 (PC=F8B4)
Stopped at watchpoint 1 reading 03 from 0000C605 (PC=FA07)
Stopped at watchpoint 1 reading 00 from 0000C603 (PC=FA07)
Stopped at watchpoint 1 reading 20 from 0000C601 (PC=FA07)
Stopped at watchpoint 1 reading 00 from 0000C6FF (PC=FA12)
Stopped at watchpoint 2 writing 84 to 0000C036 (PC=FFE2)
Stopped at watchpoint 1 reading 03 from 0000C605 (PC=FACB)
Stopped at watchpoint 1 reading 00 from 0000C603 (PC=FACB)
Stopped at watchpoint 1 reading 20 from 0000C601 (PC=FACB)
Stopped at watchpoint 1 reading A2 from 0000C600 (PC=C601)

Answer 2

In reference to the comment "Any idea how the IIGS implements those Disk II motor detectors?"

There's this Technical Note #68: Tips for I/O Expansion Slot Card Design.

It says:

On the Apple IIGS, the Mega II select signal (/M2SEL) is used as the enable to the slower, 1 MHz side of the system. It goes active (low) whenever the 1 MHz side of RAM or I/O areas are accessed. Accesses that casue the /M2SEL to be asserted include shadowed video write, any accesses to internal I/O or expansion card slots, and accesses to bank $E0 and $E1. Accesses to any expansion card ROM areas that are set to Internal ROM with the Slot register, do no assert the /M2SEL signal and run at the 2.8 MHz speed rather than the normal 1 MHz expansion card speed.

So, at a high level, it seems the the whole expansion card section is blocked out to be accessed at 1 MHz.