From the "MCS6500 Microcomputer Family Hardware Manual (January 1976)" (p. 37)
The RDY input delays execution of any cycle during which the RDY line
is pulled low. This line should change during the Phase One clock
pulse. This change is then recognized during the next Phase Two pulse
to enable or disable the execution of the current internal machine
cycle. This execution normally occurs during the next Phase One clock;
timing is shown in Figure 1.13.
The primary purpose of the RDY line is to delay execution of a program
fetch cycle until data is available from memory. This has direct
application in prototype systems employing light-erasable PROMs or
EAROMs. Both of these devices have relatively slow access times and
require implementation of the RDY function if the processor is to
operate at full speed. Without the RDY function a reduction in the
frequency of the system clock would be necessary.
The RDY function will not stop the processor in a cycle in which a
WRITE operation is being performed. If the RDY line goes from high to
low during a WRITE cycle the processor will execute that cycle and
will then stop in the next READ cycle (R/W = 1).
I'd say, given that figure 1.13 (see below) shows R/W immediately going high at the start of the reset sequence and remaining high during the entire sequence (indicating a read cycle), this should apply to any cycle of the reset sequence. Since the expressed purpose of RDY = 0 is to inhibit any fetch cycles, this should mean that when RDY goes low, the current cycle is delayed (i.e., the progression of the clock to Phase 2 inhibited) and there should be no noticeable bus activity. Compare figure 1.13 below, showing no bus activity before Phase 2 goes low for the fetch of the reset vector. However, mind SYNC (6502 specific) going high during the 3rd cycle of the sequence. (I have no idea what the implications of RDY = 0 for this SYNC spike might be.)
(Notably, this is just my interpretation of the manual and not based on empirical data.)
