I don't think your scheme is any more extensible than Intel's. It's easy to see how to widen the address space in Intel's scheme: just increase the shift value in later generations.
Of course, this will break software that tries to do arithmetic on segments assuming that the addressable space is and always will be 1 MiB, instead of treating them as opaque values to be manipulated only via OS calls and dereferencing. But your approach has the same problem. Look at the 68000: it had 32-bit address words and a 24-bit address space, and programmers used the top 8 bits of pointers for other purposes, making it difficult to extend the address space later on.
In your approach, as soon as programmers notice that segment values are always in the range 0 to 15, they'll pack them into bytes instead of words, because why waste space? And they'll use the high 4 bits of those bytes for other purposes too. When it comes time to increase the address space, there will be at least one widely used piece of software that did that, and the company that made it will be defunct or just decide it's economically infeasible to fix it, and no one will want to upgrade their hardware because they're more interested in working software than in the hypothetical benefits of future software with access to a larger address space. After all, you don't need a larger address space to access more RAM, you just need a bank-switching scheme. Sure it's ugly but it's compatible.
That's what always happens when platforms try to design for expandability.
I don't see any other advantage of your scheme that's significant enough to prefer it over what Intel did. Intel's system has an obvious advantage in terms of allocation. If you have two 40K segments, you can just put them right after one another. With 64K paragraphs, either you put the segments in separate 64K regions and hope that you'll be able to fill in the gaps with 24+24K of other data, or else every piece of software, even if it fits in 64K, has to work with far pointers and segment arithmetic just in case it's loaded spanning a 64K boundary.
Programming for a system whose registers are narrower than its address space is always going to be a pain. People blame the 8086 segment model for the problem, but it's not the problem, it's an attempt at a solution – and I think it works about as well as anything could have.