In 8086 architecture memory is addressed by segment:offset scheme, where the 20-bit linear address is formed as address=segment*16+offset. This looks needlessly complicated and doesn't allow to further extend physical address width without changing instruction set, despite the logical address having two 16-bit components (and 16+16>20).

A much simpler way seems to be address=segment*65536+offset. Also, in this case it'd be trivial to extend physical address width — by simply giving meaning to higher bits beyond originally used (lower 4 bits of segment and 16 bits of offset). Also, in such a case the CPU wouldn't even have to perform any addition to form the physical address.

Why was the actual address formation scheme chosen instead of the more straightforward one? Was it meant to say something like "any extension must be radical", like a change to 80286 addressing model?

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    Maybe something as a 256 scaling, offering 16MB of RAM could have been more sensible. 1MB was a lot of RAM at that time. Using overlapping segments makes memory use a bit more efficient. – TEMLIB Jun 25 '16 at 19:29

Wikipedia says:

According to Morse et al.,.[5] the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins

Note the 8086 was a originally intended as Intel's rather quick shot at competitor's announced 16-Bit processors. So it had to re-use a lot of existing components. In addition to the reasons mentioned by Wikipedia, I guess the original segment architecture was intended as a sliding window of 64kB over the 1MByte address space. The segment register shift determined the granularity at which the window could be adjusted. So it was a trade-off between adjustable window granularity and addressable memory space - Given it was 1976, I guess 1MByte was considered an astronomically high amount of memory, and the amount of pins was a strong argument as well.

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  • I think the answer would be even better if it linked to the particular wikipedia page from which you took the quote. – Ruslan Jun 26 '16 at 6:15
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    @Ruslan I added a link to the relevant part of the Wikipedia article. The linked document is very interesting (and has been linked here before). – Stephen Kitt Jun 26 '16 at 7:56
  • @StephenKitt The linked document claims in table 1 an address bus width of 16 for the 8086. I think this is wrong and should be 20. – tofro Jun 26 '16 at 9:19
  • @tofro I agree, the 8086 definitely had a 20-bit address bus (partially multiplexed with the 16-bit data bus). Figure 3 in Morse's document shows the 20-bit memory address latch. – Stephen Kitt Jun 26 '16 at 13:18

Using a scale factor of 16 means makes it convenient to work with objects up to 65520 bytes located on any 16-byte boundary. High-level languages don't support the concept very well, but when using machine language, rounding object sizes to 16-byte multiples makes it possible to use two bytes for object addresses rather than four. If the scale factor were larger, one would either have to round objects up to multiples of 256 bytes (rather than 16) or use 4-byte pointers (which many languages end up requiring anyway).

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  • Indeed, this allows to save memory by reducing {1. address size}, {2. minimum object size}, compared to a larger shift. It seems in fact that C could be implemented in this way (if we limit max object size to 64K). – Ruslan Jul 21 '16 at 19:37
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    @Ruslan: One could write a Standard-compliant C compiler in which all structures are required to be sixteen-byte aligned, but that would not represent a very efficient use of memory. What's needed is to have separate types for "pointer to anything anywhere" [4 bytes] and "pointer to segment-aligned object" [2 bytes] but C has no such concept. – supercat Jul 21 '16 at 21:04

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