According to Zilog Oral History, Zilog only had a tight schedule to design the Z80. Facing the potential competition, Federico Faggin and Masatoshi Shima were worrying about Japanese semiconductor corporations copying their design: if they managed to clone the Z80 quickly, it would hurt Zilog's sales significantly. As a preventive measure, Federico Faggin asked Masatoshi Shima to implant several traps in the Z80 layout, intended to mislead, frustrate, and delay any reverse-engineering effort.
Slater: You had some concerns about Japanese companies, in particular copying your design. How did you address that concern?
Faggin: Yes, we were concerned about others copying the Z80. So I was trying to figure what we could do that that would be effective, and that’s when I came across an idea that if we use the depletion load the mask that doesn’t leave any trace, then I could create depletion load devices that look like enhancement mode devices. And by doing that we could trick the customer into believing that a certain logic was implemented, when it was not. Then I told Shima, “Shima, this is the idea how to implement traps. Put traps, you know, figure out how to do the worst possible traps that you can imagine,” and then Shima with his mind, that was steel mind, was able to actually figure out a bunch of traps that he could talk about.
Slater: You want to tell us a little about that Shima?
Shima: I didn’t count [on] talking about that mostly. I placed six traps for stopping the copy of the layout by the copy maker. And one transistor was added to existing enhancement transistors. And I added a transistor looks like an enhancement transistor. But if transistors are set to be always on state by the ion implantations, it has a drastic effect on very much. I heard from NEC later the copy maker delayed the announcement of Z80 compatible product for about six months. That is what I got from NEC.
I'm aware that several groups have taken pictures of the Z80 die since then, also, some analysis has been done to reverse-engineer the chip publicly, especially the work of the ongoing, almost complete full-chip simulation from the Visual6502 team.
My question is:
Today, do we have more knowledge about those "traps"? Have they been identified and documented?
If so, what are the effects of these "traps"? Was the Visual6502 team affected by them?