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As described in the MOS 6526 CIA data sheet (at the bottom of page 5) and this answer, the PA0-7 and PB0-7 pins:

  1. always act as inputs, even when the data direction register (DDR) is set to 1 ("output") for that pin, and
  2. the outputs are open drain, so setting 1 in both the DDR and the Peripheral Data Register (PR) has the same effect as setting 0 in the DDR and any value in the PR.

So it seems that the DDR isn't really necessary; rather than writing 0 to a bit in the DDR one can just write 1 to the corresponding bit in the PR and have the same effect.

So what use is it to have these two not-strictly-necessary DDR registers? I would think that adding more registers would not make the chip design or manufacture easier or cheaper, though perhaps it could help with testing. Does it make writing certain kinds of programs significantly easier?

A note on the CIA driving its output pins:

The data sheet doesn't explicitly say whether the outputs are open drain or whether there they are driven with additional current beyond that supplied by the built-in pull-up when a pin's bit is set in both the DDR and the PR.

However, Commodore had owned MOS Technologies for several years by the time design on the Commodore 64 started and various stories I've read about the design process indicated that the C64 designers worked closely with the chip designers. Commodore seemed fine with shorting the CIA I/O pins to ground; they did this with ten different joystick switches and, via sinking current through other I/O pins, with the keyboard matrix, as you can see from the schematic on page 12 of the Service Manual.

Clearly this wouldn't be safe if the outputs were not designed to be pulled low regardless of whether the CIA is driving them or not, and the standard way to do this would be to have open drain outputs and pull-ups.

If you posit that the CIA is driving the outputs with additional current beyond that supplied by the pull-up, I'd appreciate an explanation of why you think this would be so and what advantage this might provide, given that those outputs still have to act just like open-drain outputs with pull-ups would anyway.

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the PA0-7 and PB0-7 pins:

  1. always act as inputs, even when the data direction register (DDR) is set to 1 ("output") for that pin,

Correct.

  1. the outputs are open drain, so setting 1 in both the DDR and the Peripheral Data Register (PR) has the same effect as setting 0 in the DDR and any value in the PR.

Not quite. The datasheet says:-

Port A and B have passive pull-up devices as well as active pull-ups, providing both CMOS and TTL compatibility.

The 6526 is an NMOS device, so all logic gate outputs use pullups to produce the high value. But since the pullup function is provided by an N channel MOSFET, it can only pull up to Vdd - Vgs (which may be 1~2V below Vdd). For CMOS compatibility the output high voltage needs to be close to Vdd, which is why the pullup resistors are included.
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The Port Input Pull-up Resistance is specified as typically 5kΩ, which should result in 1mA source current when the pin is pulled to ground. However when the pin is an output the typical source current is specified as 1mA at >2.4V, when the pullup resistor would only be supplying ~0.5mA. This suggests that the active pullups are only enabled in output mode.

So although setting both the DDR and PR bits to 1 will still result in being able to read a 1 on the 'input', the external device driving it may have to sink more current. OTOH, as an output the increased source current could drive more TTL gates and/or higher capacitive loads.

  • So if I understand this correctly, the pull-ups are there not because these are designed to be open-drain I/O lines, but to make this chip work with CMOS logic, and the C64 design (linked in my updated question) is just a case of "pull-ups are already there; handy!"? How can one know that it's safe to short an I/O pin to ground when it's being actively driven by its DDR and PR bits both set to 1 in the CIA? – Curt J. Sampson May 31 at 9:01
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    NMOS outputs are generally always safe to short to ground, because the current is limited to a few mA. It may not be safe with high speed CMOS or TTL (eg. 74F245 can source up to 225mA!) – Bruce Abbott Jun 1 at 0:30
  • Ah, it was my lack of understanding of NMOS outputs that was the key point I was missing to understand the design and (I guess primary) purpose of the pull-ups! – Curt J. Sampson Jun 1 at 1:12
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This is a very common configuration for general purpose I/O pins.

Output Mode

The DDR register switches the output drivers on and off. When a pin's bit is set to 1, the pin drives either high or low, controlled by the PR register. It can source of sink current. The datasheet says minimum 200uA source, 3.2mA sink, on page 3.

So shorting to GND when the line is driven high will cause at least 200uA to flow through the pin, and the datasheet doesn't actually give an upper limit. Internally it will be flowing through a transistor that will start to warm up and may eventually fail, although the typical drive strength of 1000uA is fairly low so it's probably relatively robust.

Input Mode

When the bit in DDR is 0, the drive circuit is disabled and the pin is only held high by internal pull-ups. The pull-up is a high value resistor that can easily be overcome by external devices and which will not cause high current flow if the pin is driven low externally.

The datasheet says that the pull-up resistor is typically 5k, so can "supply" 1mA. That is unusually high, typically pull-up resistors are 10 times that amount, but due to the NMOS technology it needs to be fairly strong.

Bus Mode

An additional "mode" is where the PR register is set to 0, and the DDR register is used to toggle the pin's drain capability on and off. That mode is useful for things like shared buses that should only ever be driven low.

What is the difference between output drive and the pull-up?

Driving the output high is faster than allowing it to be pulled up through a passive resistor. That allows for higher speeds, at the expense of not being able to drive some TTL loads. The passive pull-up is better for driving TTL but slower.

  • Does the CIA actually drive the bus more than the pull-up does when DDR and PR are both set to 1? What happens in that case when something like a joystick switch in the C64 shorts the line to ground? If the CIA lets the line go low, isn't the driver then doing exactly the same thing as the pullup? – Curt J. Sampson May 31 at 7:51
  • @CurtJ.Sampson Yes, as I mentioned when DDR is 1 there is drive circuitry. I'll expand a little for you. The pull-up is weak, the drive circuit is much stronger. If you short it when it is trying to drive you will cause the chip to brown-out most likely, or be damaged. – user May 31 at 7:53
  • I'm not sure that the pull-up is so weak; according to the datasheet the pull-up is between 3.1 and 5.0 KΩ and there is active pull-up circuitry as well. And the Commodore 64 design allows shorting a line driven by the CIA, as I explain in an edit to my answer. Surely they wouldn't create a design that could so easily damage the chip, would they? I believe even their own keyboard polling routine may set both DDR and PR bits to 1 when scanning the keyboard. – Curt J. Sampson May 31 at 8:10
  • Also, if you have any references to documentation on this, that would be great. I don't have any of this hardware myself, and it's obviously something that can't be properly tested in an emulator. – Curt J. Sampson May 31 at 8:11
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    @CurtJ.Sampson: Most "normal" NMOS or TTL push-pull outputs of that era had high-side drive transistors that couldn't be switched fully on (since that would require a source of a voltage higher than the normal 5V supply), and were thus far more tolerant of being shorted to VSS than low-side drivers were to being shorted to VDD. – supercat May 31 at 19:37
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1) If the DDR sets pin as output, the output data pin is a TTL push pull output and otherwise it is a TTL input with pull-up. Reading the data register does give the actual state of the pin, no matter if it is input or output. But as we are talking about TTL outputs, they are extremely weak at sourcing current. As per the datasheet, output high current is 200 to 1000 microamps. The pull-up is 5 kilo-ohms and required to get 5V output, as TTL outputs don't go much above 4V without resistive pull-ups. So even in output mode, the pin state can be easily overdriven externally to ground. But the pull-up alone will not be strong enough to drive another TTL input, so the pin must be set to output to be strong enough to drive another TTL input.

2) Datasheet does not mention anything about open drain or open collector drive. All parameters indicate it is a TTL output when set as output, and weakly pulled up TTL input when set as input.

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    The data sheet says, "On a READ, the PR reflects the information present on the actual port pins (PA0-7, PB0-7) for both input and output bits." I don't see how that's compatible with your interpretation 1). – Curt J. Sampson May 31 at 6:28
  • You're right that though the data sheet mentions a few other open drain pins, it doesn't say explicitly that the I/O outputs are open drain. I guess I had just assumed that it relied on the the pullups to supply the current. But does this make any difference? The nature of the design is that it would have work the same way anyway, allowing anything grounding that line to "win" over the CIA trying to pull it high, right? – Curt J. Sampson May 31 at 6:32
  • I will correct my statement, thank you – Justme May 31 at 10:38
  • Ok, this updated answer makes sense, but I don't see how you determined this from the data sheet. Can you tell me which particular parts of the data sheet you read to figure this out, in particular the 10 µA figure for the pull-ups? Or is this information from somewhere else? – Curt J. Sampson May 31 at 12:33
  • Sorry I misread the datasheet in a hurry - 10uA is the max leakage current. Pull-up is 5 kilo-ohms typically, it is funnily said (5 KV/A) but other datasheets confirm it Will correct it again. The pull-up needs to be there for driving CMOS chips, as TTL outputs might go only to about 4V without a resistive pull-up and that is not enough. – Justme May 31 at 17:42
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So what use is it to have these two not-strictly-necessary DDR registers?

It simplifies programming: The DDR register acts as a programmable mask to the output of the DR register.

If it wasn't there, the 6502 code (similarly for other CPUs) would have to include AND #$xx commands for every write to DR, or even more complicated constructions for biderectional pins.

So it's a convenience the hardware offers.

It's also possible that there are actual differences in the electrical characteristics, but that depends on the concrete implementation, and I haven't seen a diagram of the CIA yet (though chances are good someone on the Internet has already decapped it, and made photos).

The data sheet says

Port A and B have passive pull-up devices as well as active pull-ups, providing both CMOS and TTL compatibility.

so apparently it's not completely straightforward.

  • If I'm understanding the data sheet correctly, the DDR is not exactly a mask for writes to PR; it's a mask for the PR output; that is, the PR will still have the 1 or 0 written into it, and when a DDR bit is set to 1 the "output" value will be that of that of the most recent write, regardless of what the DDR was when that write was done. Does this affect your supposition at all? – Curt J. Sampson May 31 at 8:36
  • Also, it seems that Commodore's own code doesn't use this; the Kernal keyboard scan code assumes that DDRA (at $DC02) has been preset to $FF, which is done by the I/O initialization code. (This listing may be easier to search for addresses such as $DC02.) That doesn't necessarily mean that this feature isn't used elsewhere, of course. – Curt J. Sampson May 31 at 8:41
  • Yes, I meant mask for PR output. Corrected. – dirkt May 31 at 9:15
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[This is an attempt to summarize my understanding of the other answers. Feel free to correct this or complain if you think this restatement isn't useful.]

The misunderstanding by the OP (me) is that because a specific design (the C64 keyboard/joystick interface) uses this chip in a certain way, using it that way was the intent of the design.

The primary reason behind adding internal pull-ups to the 6526 is not to enable (or force) an open-collector style of use, as with the optional I/O pin pull-ups on a modern microcontroller such as an Amtel AVR, though it can support this (as seen above).

The data sheet points out, in huge letters at the very top, that this is an NMOS device. Earlier answers by Bruce Abbott and user and also some comments explain that NMOS when actively driving a pin: a) raises it to "Vdd - Vgs (which may be 1~2V below Vdd)", so a "high" output level will be recognised by TTL (+2.4 V min) but not CMOS inputs; and b) will supply only a small amount of current. A consequence of point b) is that, unlike CMOS or newer TTL outputs, it can be safe to short to ground an NMOS output being driven high as current flow will be limited.

Adding the internal pull-ups raises the voltage of a high output from the active circuitry, allowing CMOS inputs to recognize a high output from the 6526, and also supplies additional current, allowing the 6526 to drive larger loads (up to 2 TTL loads in this case).

So in this design DDR=1,PR=1 (actively driven) is different from DDR=0,PR=x (passively driven by the pullups) because the former will go high a bit faster and drive larger loads.

In a design like the C64 keyboard/joystick inputs the two modes may be interchangable because the only load being driven is another input on the 6526, but that would not be the case when you want to present high to a CMOS input or drive high a larger TTL load, where you must use DDR=1,PR=1.

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