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According to this answer (How did multiply instructions work in the various 68ks?) the MC68000 can take up to 70 clock cycles to multiply.

The ZX Spectrum Next's FPGA based Z80N has a MUL DE instruction that always takes 8 T-States.

How does it do that? What is the difference between how they work?

closed as off-topic by pipe, Chenmunka Jun 2 at 11:12

This question appears to be off-topic. The users who voted to close gave this specific reason:

  • "This question does not appear to be about retrocomputing, within the scope defined in the help center." – pipe, Chenmunka
If this question can be reworded to fit the rules in the help center, please edit the question.

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    How is the Z80N retro in any way? You're asking how a modern FPGA is programmed to offer fast multiplications. – pipe Jun 2 at 10:50
  • @pipe I guess it's borderline. Spectrum Next may count as a retro project, as it tries a faithful emulation. So far using an FPGA is much like any other software emulation. Sure, the CPU got a bunch of extensions but so far all within the possibilities of a 1980s 8 bit CPU. Much like a customized Z80 for some game console in 1980 might have been. AFAICT no (big) shortcut has been taken. I do as well see the valide critique that the question is a somewhat naive - as well as targeting the FPGA, which is a bit like asking for the binary code tricks of a Windows 10 based emulator – Raffzahn Jun 2 at 12:29
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    It's defintely off-topic, and it should belong to electroinc engineer stack exchange. The current answer is: UNKNOWN because the source code of the TBBlue core has not been released yet. Most probably, the core is using one or more DSP48 modules built-in the Spartan 6 FPGA they used. Each DSP48 module has a multiplier and an adder, so the hardware description of a product in Verilog can be expressed with just the product of two signals, and this will take 1 clock cycle. – mcleod_ideafix Jun 2 at 13:01
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    I'm not sure why this question is being re-opened. It has been edited, and the edit is good, but the premise of the question is still about a modern implementation of an architecture. The question is still off-topic. Remove the parts about the Z80N, and make it exclusively about the 68000 multiply, and the question and current answer would be fine. – DrSheldon Jun 2 at 15:29
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The MC68000 can take up to 70 clock cycles to multiply.

The ZX Spectrum Next's Z80N has a "mul de" instruction that always takes 8 T-States.

It's 'only' an unsigned 8x8 multiplication, as the 8 bit registers D and E will be multiplied and the 16 bit Result stored in DE, while the 68k multiplications (MULS being the signed version) is a 16x16 multiplication.

How does it do that? What is the difference between how they work?

By the Z80N MUL being a more simple operation and at the same time throwing much more hardware at it?

The 68k MULU/MULS is implemented in micro code, as adding a hardware multiplier would have enlarged the CPU quite a lot.

The Spectrum Next is build using an Xilinx Spartan-6 FGPA (Type XC6SLX 16), a chip with SEVERAL TEN THOUSAND TIMES or maybe even more than HUNDRED THOUSAND TIMES (depending if the RAM is counted) the transistor count of an 68000 (which itself is already about 7 to 8 times as much as the original Z80). Easy to offer 8x8 bit hardware multipliers with a monster like that.

In fact, it's safe to assume that it could be way faster than the 8 T-States, as these seam to be in line with the RMW nature of the instruction. All to make them work out in a comparable relative timing as the real Z80. Given the hardware such an FPGA provides, eZ80 like timing or even lower can be easy archived - ofc, this would make it hard to slow it down to play timing dependant games from a real Spectrum :))

Bottom line: It's simply the result of 40 years of Moore's Law.

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    I'm pretty sure MULU and MULS are available only in 16x16 form on the original 68000. The 32-bit forms are from the 68020 onwards. I wish I had more to contribute than this, but you've covered everything else comprehensively as ever. – Tommy Jun 1 at 23:06
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    In fact the z80n multiply can complete in a single 28MHz cycle which is the top clock speed in the system. The 8T time is solely due to the opcode fetch of two bytes which must take that amount of time in a z80 system. As already mentioned, it is moore's law in action. When the 68k was made they likely did not want to spend a lot of space on a single cycle hardware multiply and instead performed the operation as a sequence of steps using less hardware which took more time. – aralbrec Jun 2 at 4:42
  • While the spartan 6 likely has (at an educated guess) 15000 times as many transistors as a 68k, it's not true the transistor count is directly comparable. In an fpga, the transistors are used to implement a generic logic fabric as well as hold configuration information in sram cells, control routing with pass transistors, and so on. In short a lot of transistors are not being applied to directly implement the logic. Because the logic is generic, only a fraction of the logic is actually useful in a completed design. – aralbrec Jun 2 at 6:14
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    As an aside, the Motorola 6809 had a MUL instruction. It took A * B (both 8 bit) and stored in D (16bit, using A+B). This instruction took 11 cycles. techheap.packetizer.com/processors/6809/6809Instructions.html – CSM Jun 2 at 11:12
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    @Tommy You're of course right, it's a 16x16 and it wasn't until the 020 that a 32x32 was added. Sorry. I should always check the manual, not just my memory. – Raffzahn Jun 2 at 12:19

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