I'm trying to make a 6502 replica in Logisim. I want to know what exactly each control signal in 6502, how the clock cycles work and additionally I would like to see an example of these control signals producing a single instruction from start to finish.

Is there a book about 6502 or other processor that goes in depth about it's control signals? If not, maybe you could shed some light on my question?

  • Check out visual6502.org/JSSim/index.html
    – Brian H
    Commented Jun 3, 2019 at 21:09
  • 1
    I know this site. But I don't know a lot of terminology. I believe it has all the control signals, but their names alone don't give me anything. I'm asking for explanation to what they are and what they do. Maybe there's an article about it on the internet, but I wasn't able to find what I need for a long time now.
    – Senijs
    Commented Jun 3, 2019 at 21:16
  • Do you mean its internal or external control signals?
    – JeremyP
    Commented Jun 4, 2019 at 13:52

2 Answers 2


I can give you an overview of the external control signals that appear on the pins of the 6502, but you'll need to go to somewhere like visual6502.org to get an idea of the internal signals.

There are three control signals dedicated to the clock

  • ø0
  • ø1
  • ø2

The first is an input, the system clock. ø1 is an output: ø0 inverted but with the high pulse slightly shortened. ø2 is the same as ø0 again with the high pulse slightly shortened. When ø1 is high, the processor is doing internal processing stuff and setting all the output pins (except data pins for writes which it does during ø2 according to the timing diagrams) into the correct state for the following ø2 pulse. When ø2 is high, the CPU is doing a memory access. The reason why ø1 and ø2 have shortened high pulses is so that they don't overlap and cause ambiguity about what the processor is doing and what the state of its output pins is.

The 6502 does a memory access in the second half of every ø0 clock cycle, even when it doesn't need to. This is important to understanding the internals and some of the quirks of the instruction set.

Other signals associated with memory accesses are:

  • R/W which the CPU sets high to read and low to write.
  • SYNC which is set high when opcodes are being read.
  • A0 - A15 the address bus
  • D0 - D7 the data bus

There's also

  • RDY, which, if you set it low, will cause the processor to freeze at the beginning of the next ø2 as long as it is a read cycle. If you set RDY low when SYNC is high, you can single step the processor.

There are two inputs associated with interrupts

  • IRQ which causes interrupt processing to start (at the end of processing the current instruction) if it is driven low. IRQ can be ignored programmatically by setting the interrupt flag in the status register.
  • NMI which causes interrupt processing to start (at the end of processing the current instruction) if it is driven low. NMI cannot be disabled. Note that NMI is edge triggered because otherwise the processor would continuously interrupt until you let NMI go high again.

There's also

  • Reset which effectively stops the processor when it goes low and then restarts it (from scratch like when it has just been turned on) when it goes high again.
  • SO which sets the overflow flag in the status register when you drive it low during the second half of ø1.

I think that's all of them for the 6502.

During a typical read cycle, in ø1 the processor will

  • set R/W to high to signal a read
  • set the address pins
  • configure the data pins to read
  • set SYNC to high if the CPU is reading an instruction, or low otherwise
  • check to see if SO transitions from high too low and set overflow if it does

In ø2 the processor will

  • check that RDY hasn't transitioned from high to low and temporarily halt the processor if it does
  • read the data pins

During a typical write cycle, in ø1 the processor will

  • set R/W to low to signal a write
  • set the address pins
  • configure the data pins to write

In ø2 the processor will

  • write to the data pins
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    I meant the internal pins, yes. But I don't know much about the external ones either, so thanks for this!
    – Senijs
    Commented Jun 5, 2019 at 8:27
  • The separation between phi1 and phi2 isn't just to avoid "ambiguity", but plays a role similar to a fork-based clockwork escapement. When either prong of the fork is withdrawn, it will allow the escapement wheel to advance until it contacts the other prong, but if both prongs were ever withdrawn simultaneously the escapement wheel would spin wildly out of control.
    – supercat
    Commented Dec 7, 2021 at 20:25
  • 1
    Your answer is better than most of blog posts and materials about 6502 in the internet. Thanks a lot - it helped me a lot.
    – ytropek
    Commented Nov 14, 2023 at 19:54

I'd just go with the datasheet (Rockwell version, Commodore Version) as it contains everything needed. But there is THE book to read:

The MOS MCS6500 Family Hardware Manual

One hint, in all respect and seriousness, if you have a hard time to give the signals a basic meaning (as noted in your comment), then simulating a CPU might be above your level.

  • 1
    I have simulated a CPU before. What I meant to say in my comment is that I don't know what 6502 specific control signals do. And they have weird names. I'll check out the book you gave me, perhaps it has the explanation on the control signals' names and their function?
    – Senijs
    Commented Jun 3, 2019 at 21:36
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    @Senijs The 6502 Names are in line with many other CPUs of the same time and class. Nothing really out of the ordinary. Try to read the data sheet it tells everything 6502 specific - that is if you know the terminology of that time.
    – Raffzahn
    Commented Jun 3, 2019 at 21:42
  • Thanks for that. I most likely will have to google a lot of terminology in that book tho.
    – Senijs
    Commented Jun 3, 2019 at 21:50

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