How exactly do all control signals in 6502 work?

Question

I'm trying to make a 6502 replica in Logisim. I want to know what exactly each control signal in 6502, how the clock cycles work and additionally I would like to see an example of these control signals producing a single instruction from start to finish.

Is there a book about 6502 or other processor that goes in depth about it's control signals? If not, maybe you could shed some light on my question?

Answer 1

I can give you an overview of the external control signals that appear on the pins of the 6502, but you'll need to go to somewhere like visual6502.org to get an idea of the internal signals.

There are three control signals dedicated to the clock

• ø₀
• ø₁
• ø₂

The first is an input, the system clock. ø₁ is an output: ø₀ inverted but with the high pulse slightly shortened. ø₂ is the same as ø₀ again with the high pulse slightly shortened. When ø₁ is high, the processor is doing internal processing stuff and setting all the output pins (except data pins for writes which it does during ø₂ according to the timing diagrams) into the correct state for the following ø₂ pulse. When ø₂ is high, the CPU is doing a memory access. The reason why ø₁ and ø₂ have shortened high pulses is so that they don't overlap and cause ambiguity about what the processor is doing and what the state of its output pins is.

The 6502 does a memory access in the second half of every ø₀ clock cycle, even when it doesn't need to. This is important to understanding the internals and some of the quirks of the instruction set.

Other signals associated with memory accesses are:

• R/W which the CPU sets high to read and low to write.
• SYNC which is set high when opcodes are being read.
• A₀ - A₁₅ the address bus
• D₀ - D₇ the data bus

There's also

• RDY, which, if you set it low, will cause the processor to freeze at the beginning of the next ø₂ as long as it is a read cycle. If you set RDY low when SYNC is high, you can single step the processor.

There are two inputs associated with interrupts

• IRQ which causes interrupt processing to start (at the end of processing the current instruction) if it is driven low. IRQ can be ignored programmatically by setting the interrupt flag in the status register.
• NMI which causes interrupt processing to start (at the end of processing the current instruction) if it is driven low. NMI cannot be disabled. Note that NMI is edge triggered because otherwise the processor would continuously interrupt until you let NMI go high again.

There's also

• Reset which effectively stops the processor when it goes low and then restarts it (from scratch like when it has just been turned on) when it goes high again.
• SO which sets the overflow flag in the status register when you drive it low during the second half of ø₁.

I think that's all of them for the 6502.

During a typical read cycle, in ø₁ the processor will

• set R/W to high to signal a read
• set the address pins
• configure the data pins to read
• set SYNC to high if the CPU is reading an instruction, or low otherwise
• check to see if SO transitions from high too low and set overflow if it does

In ø₂ the processor will

• check that RDY hasn't transitioned from high to low and temporarily halt the processor if it does
• read the data pins

During a typical write cycle, in ø₁ the processor will

• set R/W to low to signal a write
• set the address pins
• configure the data pins to write

In ø₂ the processor will

• write to the data pins

Answer 2

I'd just go with the datasheet (Rockwell version, Commodore Version) as it contains everything needed. But there is THE book to read:

The MOS MCS6500 Family Hardware Manual

One hint, in all respect and seriousness, if you have a hard time to give the signals a basic meaning (as noted in your comment), then simulating a CPU might be above your level.