Why VGA framebuffer was limited to 64kB window?

Question

VGA framebuffer was fixed to 64kB at A0000h. Right after that there’s MDA/CGA framebuffer at B0000h. I am not sure, but I recall VGA did have to support CGA and its framebuffer, but was there any reason why VGA couldn’t use eg 128kB (ie segments A and B) as linear framebuffer for modes such as 320x240x8b?

ModeX and others do imply all VGA boards must’ve had more than 64kB of video ram on board, but it had to be accessed via bank switching. Since VGA would need to claim ownership of B segment for CGA compatibility (but this is not needed if using VGA display modes), I cannot see any reason why they did resort to bank switching.

Answer 1

The VGA design is inherited directly from the EGA design, though with a few extra features. Most considerations apply equally to both.

Although it is possible to treat the EGA or VGA memory as four banks of 65,536 octets, the EGA was designed to let it be treated more usefully as 65,536 groups of four octets, where each group had a single assigned CPU address. Within each group of eight pixels, each pixel would use one bit taken from each octet. The EGA and VGA have a 32-bit buffer that gets loaded from all four groups of pixels whenever an address is read, and each write will store to each group of 32 pixels a pattern which is based upon the value written, the value of some configuration and parameter registers, and the contents of the buffer.

This made it possible to perform many kinds of read-modify-write operations on a group of pixels at a time. The CPU would read a byte, ignore the result, and then write a value that indicated how the group of bytes should be modified. The display card would then combine the value in the buffer with the value that was read and store the modified result to all 32 bits. This allowed for bytes in display memory to be updated with a single read-modify-write sequence.

Alas, a couple aspects made this design far less useful than it could have been. They largely boil down to the fact that for various technical reasons, reading display memory is extremely slow, and every action on a group of 32 pixels would require four individual read-write sequences. If the computer had enough "main" RAM to maintain a copy of the screen, building the display contents in RAM and blindly outputting to the display would almost always be faster than trying to use the display's hardware to expedite the process. On slow machines the display hardware could offer some speed advantage, but as main-CPU speed increased the extra display hardware became more and more useless.

Still, the designers of the EGA and VGA had expected that the ability to update multiple bytes at once would be useful, and thus designed their architecture to facilitate it.

Answer 2

When VGA was designed and released, it had only maximum of 256 kbytes of video memory. The memory of VGA is arranged to have 32-bit interface to the VGA chip to have four byte planes in parallel. Therefore there are only 64k addresses of 32-bit video memory, and data of up to four planes can be accessed with a single CPU access.

The VGA board can be configured for a 128k framebuffer at A0000h, but both 64k segments will access the 64k addresses of video RAM identically. The trick that makes standard Mode 13h look linear is implemented in hardware, it only uses every fourth address of video memory, and automatically selects the plane based on lowest 2 CPU addresses. Unchained modes need manual plane selection in software when writing to video memory. It would have taken extra logic to make the whole video memory look like linear, and this was just not so important as it already was quite complex and it was enough make it compatible with EGA.

So in short, the VGA hardware is made to have four bytes accessible via single CPU address so there are only 64k memory addresses the CPU can access.

Answer 3

In the 16-bit 8086, addressing of the memory space was done with a two-register pair Segment:Offset. The Segment register (there were four of them) addressed the high 16 bits of the 20-bit addressable memory, and the Offset register addressed the low 16 bits. So The effective address was computed in the CPU by:

EA = 16 * Segment + Offset

So, in order to address more than 64k of memory at once, software would have to change the segment register as well as the offset. This was very inefficient in the CPU, and it was much better to limit memory block access to 64k at a time. The video card designers recognized this, and built the hardware with bank switching so that software would not have to change the CPU segment register to address the whole display memory.