I believe the 80286 had a prefetch instruction queue, but did it have any other forms of cache? Was the 80386 the first x86 CPU to have a cache?

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    Even the 8086/8 had a prefetch instruction queue, which was notably used for some entertaining debug/reverse engineering protection schemes involving self-modifying code... Commented Jun 5, 2019 at 12:35
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    @Brian including this amusing example recently unearthed by the DOSBox-X developer! Commented Jun 5, 2019 at 12:47
  • And there were caches long before x86, e.g. the CDC 6600 and the IBM 360 had "instruction buffers" (a pre-fetch region large enough in some models to call it an instruction cache, and not a queue).
    – dirkt
    Commented Jun 5, 2019 at 12:47
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    @dirkt even in the micro-processor world, with e.g. the Z80000 in 1983 and the 68020 in 1984 (and those could easily not be the first). Commented Jun 5, 2019 at 12:49
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    For the historical record, Wilkes invented the cache, then called a 'slave memory', which he published in 1965. But this question is about the x86 series.
    – dave
    Commented Apr 9, 2020 at 11:42

2 Answers 2


The 486, introduced in 1989, was the first x86 CPU to include a cache. It added cache-supporting instructions to the x86 ISA such as INVD and WBINVD.

The 386 didn’t have an on-board cache, but it could be associated with an 82385 controller to use an external cache. Some later 386-compatible CPUs, such as IBM’s 386SLC, included on-board cache; Intel’s own 386SL CPUs included a cache controller, but I don’t think they were available with on-board cache (there are conflicting opinions on the Internet). There were also 386 replacements such as Cyrix 486DLC upgrade processors, with on-board cache; since they were upgrade processors, they ended up having to deal with various cache coherency issues in ways Intel hadn’t planned for, since motherboard implementers didn’t necessarily take cache requirements into account.


(Regarding 80286 and in addition to Stephen's Answers)

While the 286 didn't have an on chip cache, some high end machines did add one. Similar for accelerator boards for 8088 PCs.

The issue here is that an 80286's memory cycle was, at the time, still slow enough to be served with widely available standard RAM. The 286 uses two full clock cycles (PCLK) to access memory. Thus an 8 MHz CPU needs RAM with a 200ns access time or better.

Also, wait states didn't break down an 80286 as much as one would assume. A 1 ws memory only slowed down the system by 10-30%, depending on the task. With one wait state A 12-14 MHz CPU could run with the same memory as an 8 MHz system, still delivering a noticeable performance increase.

Later, faster systems (12..16 MHz) employed various tactics to relief memory stress, for example interleaved banks and variable wait states. This resulted in close to maximum performance without the need of a cache.

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