Early DRAMs have a multiplexed address bus. Briefly speaking, to access a word, one needs to...
Put the row address on the bus, and latch it using the falling edge of
Put the column address on the bus, and latch it using the falling edge
The data appears at the data bus after a delay, i.e.
The above process is shown in this timing diagram:
However, in the Mostek 4116 DRAM datasheet, Column Address Set-up Time, a.k.a
t_ASC, the time between a valid column address and the falling edge of
/CAS, is a negative number. In other words,
/CAS is allowed to start falling even before the column address is stable, up to 10 nanoseconds.
This is especially problematic when interfacing devices designed for 4116 DRAM. One classic example is Texas Instruments TMS9918 video chip, of which the chip actually does start pulling
/CAS low before the column address is stable. Artificial delay must be introduced to interface it with newer RAM chips.
In comparison, in the the datasheet of a modern CMOS DRAM, Oki MSM514256C, a 256K x 4-bit DRAM (circa. 1997),
t_ASC is 0 nanoseconds, which basically means the
/CAS is only allowed to fall as soon as the the column address is valid, which is more intuitive.
I know a negative set-up time is sometimes used in digital devices, but what is the specific design rationale of having a negative Column Address Set-up Time in 4116 DRAMs? Is it simply a side-effect (e.g. propagation delay?) of the logic details used in 4116? Is it designed to allow the timing requirement to be met more easily? A faster access speed? Or it's something else?