I'm not allowed to comment, so I'll add this here. The ROM overlay reset 'hack' was not limited to 68000's, and was well-established in the industry by the time the 68000 was introduced. (Intel 8080 systems did this, as did 8085 and Z-80 successors.) The usual reason is that reset and interrupt vectors are located together, and that (for interrupts, at least) they're really only useful if they can be changed, which means they need to be in RAM. Mapping ROM over RAM, at least for a few cycles after reset, means that the system can startup cleanly in ROM and then bootstrap itself to RAM-based operation, maintaining full flexibility. It had nothing to do with rushing product to market.
Processors that did NOT do this, e.g. 6800 and its successor the 6502, theoretically were 'easier' to design into a system, yet ended up harder to use in practice for general-purpose systems because the vectors were immutable. Given that the Intel-style 'hack' was only a couple of flip-flops in the address decoder, which was almost certainly discrete logic at this point in time in the industry, the cost was nearly negligible in order to self-start and yet be maximally flexible. It is most telling that Motorola, whose first effort (6800) put the vectors in ROM space (as in: far from the RAM addresses, which would have been page zero), in their next effort (68000) did it the Intel way.
I have no idea why Sinclair did not use this well-established technique in the QL.
CP/M TPA started at 100h in order to avoid the RST/interrupt vectors. Even when using the Z-80's IM2 enhanced interrupt system, you still needed to support the RSTx instructions. It would have been a woeful computer indeed that prevented you from using some valuable instructions because the system designer had not done his homework!
By adding the VBR in the 68010+, virtualization became possible. (All of the 68010 changes were to support virtual memory and virtualization, with the exception of the performance-oriented 'loop mode'.) Otherwise you'd have to engage in a massive 1kB swap-in/out to change the entire vector table for every context switch, while disabling ALL interrupts for the duration, and likely while editing some of them to keep the virtual host behavior while merging with target behavior. Very messy. VBR was not done for the convenience of any particular customer.