13

The Intel 8086 CPU uses memory segmentation, which means that when, for example, you write the value 123 to the memory address 1001, the memory address 1001 will actually get converted first into another real memory address and then the value 123 will be written to that real memory address.

Now I have read that the Intel 8085 CPU does not use memory segmentation, so does that mean that when you write the value 123 to the memory address 1001, the value 123 will actually be written to the memory address 1001, or does the Intel 8085 CPU use some other mechanism (other than memory segmentation) to convert the memory address 1001 to another real memory address?

  • i8085 is the same as i8080 (its not related to i8086/88) the difference to i8080 is that i8085 need just +5V input voltage. – Spektre Jul 17 at 8:13
  • 1
    You seem to be confusing segmented addressing with virtual memory. On the 8086, an instruction would not access plain address 1001, but CS:1001 or DS:1001 or SS:1001. In virtual memory, the page mapping depends on high bits of the address. In a segmented model, the page mapping depends on the instruction encoding. – Ben Voigt Jul 18 at 3:56
27

The 8085 is effectively the same as the 8080 microprocessor. The 8080 has a flat 16-bit address space and no segment registers. So yes, the 8085 uses real memory addresses without any translation.

14

Simply Yes.

A basic 8080/85 (or Z80) does just output the 16 bit address generated by an instruction. There is no inherent translation, Segmentation or whatsoever.

5

We might speak to what happens within the CPU and what happens or can happen external to the CPU.

Between the CPU and memory subsystem, there is an address bus and a data bus (among some other signals that indicate when to read or write).

Each new CPU defines the number of address pins it provides, and this width (count) of the address bus (pins) generally defines the maximum size of the address space, hence size of memory.

The data bus width generally says something about the performance, e.g. an 8-bit data bus means two transfers are required to transfer a 16-bit value to/from the memory subsystem, while a 16-bit data bus means a single transfer can do an 8- or 16-bit value.

The 8080 and 8085 processors have 16 address pins.  They place the register or computed effective address directly on these address pins.  (Technically, what happens after that is up to the memory subsystem.)

The 8086 has 20 address pins.  Since it is basically a 16-bit machine, the extra 4 bits have to come from somewhere, and the answer of course is the segment registers.  They are added (in a shifted-by-4 bit position) to the 16-bit effective address that was computed by the addressing mode, to produce a full 20 bit address for the address bus and hence the memory subsystem to see.


Systems well before the 8080 and well after the 8080 supported one form or another of address translation external to the CPU, so an MMU (memory management unit) might be interposed between the CPU and main memory.  Of late, though very sophisticated MMU functionality is incorporated into the CPU.

5

The Intel 8085 CPU can only send out 16-bit addresses.

What happens to those 16-bit addresses is out of the control of the CPU.

In a normal system, some number of those bits would be sent to every RAM and ROM chip in the machine. At the same time, the remaining bits would be passed to a decoder chip which has one output going to each of those memory chips. According to the bit pattern, one of those outputs would say “ENABLE - please output the 8 bits of data corresponding to the address you are seeing” and all the others would say “DISABLE - do nothing and ignore the address”.

I said that the decoder acts according to the address bits it receives. This is not true. The decoding subsystem also has a state. To take one universal example: when the machine is switched on, it is in a “startup” state. In that state the decoder will send ENABLE to the ROM for certain addresses. This is how the system can start up at all: the ROM contains the initial program instructions.

Once the system has started, it is in a “run” rather than a “startup” state. In that state, the ROM never receives ENABLE: one of the RAM chips receives it instead.

In 8080/8085/Z80 systems, the setting of the “startup/run” state is done by outputting a value to an I/O port using the OUT instruction. Which port, and which value, is decided by the designer of the machine.

Once you have this mechanism, and once RAM has got cheaper, there is nothing to stop you switching not between ROM and RAM but between RAM and RAM. For instance, in a multitasking operating system such as MP/M or TurboDOS, you could organise things so that the top 16KB of memory addresses will always enable the same memory chip(s), while the remainder of the addresses will enable different memory chip(s) depending on what value had most recently been written to the special output port. To switch between one “bank” of chips and another thus means: output a new bank number to the special output port.

This is more or less an equivalent to loading a segment register in the 8086.

If you search for “Z80” and “bank switching” you will see many thorough and authoritative articles on the subject.

And to revert to your original 8085 question: no, the 8085 chip had no memory management, and yes, an 8085system could have as much memory management as its designer felt like including.

4

Depends on the memory subsystem and what you mean by "real memory" and memory address. It's possible some 8085 systems had multiple external memory banks (e.g. totaling more than 64 kB) switched by an external register. Switchable ROM overlays were common, not sure about RAM. The bank switch pins might or might not be called address pins, but they do the same thing, in terms of selecting which bits of actual physical RAM to read or write, beyond what was in the instruction write target value.

2

In fact, both the 8086 and the 8085 use real addressing.

The 8085, like the 8080, has a 16-bits address space from $0000 to $FFFF (65536 bytes). You can use any 16-bit register to hold an address, or push 2 bytes on the stack and return, use them in jumps etc. A 16-bit value in an addressing instruction or register directly matches a precise byte of memory or at least, a direct 16-bit address in addressing range. The actual hardware behind the bit pins of the CPU can interpret them differently, as it happened on various micro-computers of the 1980 era which sometimes had memory bank-switching systems. But the CPU addressing is a real-address scheme.

It's also a real-address scheme in the 8086 and its 80186 successor. Intel used segmentation with a 16-bit segment register and a 16-bit offset register, but the 8086 actually uses real addresses in the 20-bits space $00000 to $FFFFF (16 * 64 Kilobytes = 1 megabyte). The actual, real address is formed by shifting the segment register 4 bits to the left to make it a 20-bits value and adding the offset address. For example, the segment $1000 and the offset $2345 leads to the actual 20-bits address $10000+$2345 = $12345. The CPU pins outputs the final 20 bits on the address bus, there are not separate pins for the segment register content.

This "pseudo" segmentation has been criticized in its time because it let the programmer think/feel a segment is isolated from another one, which is absolutely NOT true. For instance, both $1000:$2345 and $1234:$0005 represent the same actual address $12345. There are less obvious examples such as $8800:$9f65 and $9100:$0f65.

Non-real addressing in Intel processors started with the 80286.

0

Not sure if it is applicable, but... there is a computer system that runs with Z-80 (which is a close relative to 8080/8085). It can map up to 4Mb of memory in a 16-bit address linking 16Kb pages into the CPU bus listening to a port (or a memory position), and the CPU doesn't even know about it:

https://www.lavandeira.net/2016/07/multi-review-msx-memory-mapper-mega-mapper-and-memory-samurai-part-1-of-2/

So, there are a number of ways to accomplish a memory mapping without direct CPU support, just hot-pluggging memory pages into CPU directly, through a hardware switcher. It was made for MSX, but I don't recall something like this on the IBM world.

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