Based on my understanding, the bitness of a CPU specifies how much memory it can address (which is determined by the size of the CPU's address bus I guess). For example: a 32-bit CPU can address 232 bytes of memory.

But why is the Intel 8086 CPU called a 16-bit CPU even though its address bus is 20-bit, shouldn't it be called a 20-bit CPU?

Addendum: There is a somewhat similar question about bitness and marketing of the Mega Drive: Why was the Sega Genesis marketed as a 16-bit console?

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    Wikipedia: All internal registers, as well as internal and external data buses, are 16 bits wide, which firmly established the "16-bit microprocessor" identity of the 8086. – Kelvin Sherlock Jul 18 '19 at 0:07
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    The 6502 has 16 address pins but it's not a 16-bit cpu. The 6507 (Atari 2600) had 12 address pins but it's not a 12-bit cpu. – Kelvin Sherlock Jul 18 '19 at 0:13
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    Also 808286, 386SX and Motorola 68000 CPUs all have only 24 bits of address bus, yet they are never ever referenced as 24-bit CPUs. – Justme Jul 18 '19 at 8:08
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    Do you have reference that the address bus width is what decides the bitness of the processor? – UncleBod Jul 18 '19 at 15:48
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    This would be confusing as hell since old 32bit pentiums had PAE which allowed it to address up to 52 bit (48 being the most ever implemented) and current 64bit x86_64 CPUs essentially having a 48bit addressing scheme, but depending on model and manufacturer you only see 46 or even only 40 bits implemented in hardware actually. – PlasmaHH Jul 19 '19 at 9:41

Generally, the "bitness" of a CPU is determined by the usual or common size of its data registers (or, the width of its data bus), rather than the width of the address bus. There are exceptions, for example while the 8086 is considered a 16-bit CPU because it has a 16-bit data bus, the 8088 (which is software compatible with the 8086 and is also a 16-bit CPU) only has an 8-bit data bus which was less efficient. But functionally, it works just like the 8086.

Today's common 64-bit CPUs have 64-bit wide data registers and data bus, but the address bus isn't anywhere near 64 bits (that would be wasteful, because there isn't 2^64 bytes of memory that has ever been manufactured, let alone installed in one system).

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    IMO it is more accurate to refer to the actual register size than the data bus size. Then exceptions to the "data bus" definition, such as the 8088, don't occur. – RichF Jul 18 '19 at 1:04
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    @RichF: While that is true, there are also exceptions there. For example, the 8086 specially treats the DX and AX registers together as one 32-bit value for the purposes of some instructions (MUL, DIV). That's why I said "usual or common size". – Greg Hewgill Jul 18 '19 at 1:07
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    Is this really true re 2^64 memory never having been manufactured? That's 4B 4G systems - seems reasonable... – dashnick Jul 18 '19 at 3:00
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    @RichF Register size can be misleading. For example, the registers of the 68000 are 32 bits wide but the internal data paths, the database and the ALU are only 16 bits.The 68000 is a 16 bit implementation of a 32 bit architecture. – JeremyP Jul 18 '19 at 6:28
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    @manassehkatz: There are over 4 billion people using mobile phones. Even cheap mobile phones usually have 8GB of memory. So Greg's claim is probably false just from mobile phones alone, and definitely false overall. – BlueRaja - Danny Pflughoeft Jul 18 '19 at 16:08

But why the Intel 8086 CPU is called a 16-bit CPU even though its address bus is 20-bit, shouldn't it be called a 20-bit CPU?

Address bus size is probably the least used method to determine CPU "size". For example, the Z80 and many other CPU chips that are commonly considered 8-bit, has a 16-bit address bus. That allows easy access to 64k of memory, which was the norm for many years for typical 8-bit CP/M systems (and many other systems). If the address bus determined the "CPU size" then either these would have been called 16-bit systems or the systems would have been limited to 256 bytes of memory. Similarly, the 4-bit 4004 operated on 4-bit words but had a 12-bit address bus and could access 4k of memory - actually a little more - 4k ROM plus 640 bytes of RAM.

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    Exactly. One would be hard-pressed to find an "8-bit" processor with an external 8-bit address bus. – DrSheldon Jul 18 '19 at 6:04
  • Odd. In my computing experience I have always regarded the virtual address size as being the major determinant of "bit size", as a consequence of being concerned more with "how large can my code be?" than "how large can integers be?". – another-dave Jul 18 '19 at 12:43
  • @another-dave: That's probably because you're used to 32 and 64-bit systems, where registers are wide enough to hold a pointer. (And maybe some 16-bit systems? 16 bits is enough address space to be useful, while 8 isn't for most things). And yes, a large motivation for the move from 32 to 64-bit computing was larger address-space to work with more data. But below 16 bits, systems still usually wanted 16-bit address spaces even if everything else was narrower to save transistors. So addressing memory had to be supported with special architectural features, not like the C model. – Peter Cordes Jul 19 '19 at 17:18
  • @PeterCordes The MC6809/HD6309 family is an example where both the ALU registers and address bus are 16 bits wide. It was used in the Tandy CoCo series and the Dragon clones of it. – Chromatix Dec 1 '19 at 11:21

Why is the Intel 8086 CPU called a 16-bit CPU?

Because that’s how Intel marketed it. The 8086 is part of “the range of 16-bit processors from Intel” (see for example Introduction to the iAPX 286, page 3-1). The 8086 Primer says “In 1978, Intel introduced the first high-performance 16-bit microprocessor, the 8086.”

The 8086 Family User’s Manual isn’t quite so categorical, but it does describe the 8086 as an “8/16 bit general-purpose micro-processor” with a “16-bit external data path”; and it specifies that all CPUs in the 8086 family “operate on both 8-and 16-bit data types” with “internal data paths are at least 16 bits wide”. Regarding the 8086 and 8088’s execution units, “A 16-bit arithmetic/logic unit (ALU) in the EU maintains the CPU status and control flags, and manipulates the general registers and instruction operands. All registers and data paths in the EU are 16 bits wide for fast internal transfers.” (The EU is the execution unit.) Finally, “Both CPUs have the same complement of eight 16-bit general registers.”

This covers all the sizes which are, in various combinations, typically used to determine a CPU’s “bit-size”:

  • the internal data path;
  • the native data types;
  • the (integer) register width;
  • the ALU width.

The address bus wasn’t used to qualify a CPU’s size: the 8008, 8080, and 8085 were all considered 8-bit CPUs, even though the 8080 and 8085 had 16-bit address buses. Likewise, the 286 was marketed as a member of the 16-bit family, with a 24-bit address bus.

The address bus can in some ways be thought of as an implementation detail, as can the internal data path size. Thus, Pentium CPUs have a 64-bit internal data path, and Pentium Pro CPUs have a 36-bit address bus, but they are 32-bit CPUs; and current 64-bit x86 CPUs don’t have 64-bit address buses. Even on the 8086, the address bus only affected the bus interface unit. So using the address bus or even the internal data path size can be misleading; Intel only highlighted the latter in the 8086’s case because they were guaranteeing that it would be wide enough to transfer the native data types without splitting them up.

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  • You are certainly right that the bit-ness of a processor is all about marketing. It is whatever number that is (1) high enough so it looks at least as good (if not better) than competitors' processors, but (2) low enough that you can later sell a "better" one. – DrSheldon Jul 18 '19 at 15:48

Based on my understanding, the bitness of a CPU specify ...

One extreme example is the NS16032 or NS32016:

The CPU was first sold as "16-bit CPU" named "NS16032".

Later, the manufacturer decided to sell exactly the same CPU as "32-bit CPU" under the name "NS32016".

This example shows that there is no real objective criterion that decides if a CPU is a 16- or a 32-bit CPU.

Another example is the Infineon XC2000 which was marketed as "32-bit CPU" some years ago although the derivative I was working with had 16- and 40-bit registers but (as far as I remember) absolutely nothing which was 32 bits wide.

... how much memory it can address.

I have heard of different criteria why I CPU is seen as 16- or 32-bit CPU.

However, I never saw that anybody used this criterion!

Most CPUs I know do not have its "bitness" as address bus width:

Modern 64-bit PC CPUs have 48 bits address bus width which means that they can access 2^48 bytes of memory...

Why the Intel 8086 CPU is called a 16-bit CPU?

There are three common criteria to define the "bitness" of a CPU:

  1. The width of the data bus
  2. The width of general purpose registers
  3. The width of operations (e.g. the CPU can perform a 16-bit addition)

There are a lot of examples of CPUs where these three criteria lead to different results:

  • Motorola 68000, Intel 80386SX, NS16032/NS32016
    (16 bits according to 1., but 32 bits according to 2. and 3.)
    This explains why NS could sell the CPU as "16-bit" CPU first and later sell it as "32-bit CPU".
  • Intel 8088 (8 bits according to 1., but 16 bits according to 2. and 3.)
  • Zilog 8000 (16 bits according to 1. and 2., but 32 bits according to 3.)

However, the 8086 is a "16-bit CPU" according to all three criteria!

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  • 68000 had a 16 bit ALU. Although it had 32 bit arithmetic operations, these were performed in two 16 bit chunks as evidenced by the fact that the 32 bit versions of the operations took longer. So by criterion 3, the 68000 is a 16 bit CPU in implementation. – JeremyP Jul 18 '19 at 7:28
  • @JeremyP Not really, as the operations performed are 32 bit. Point 3 doesn't state if it's to be done parallel or serial. – Raffzahn Jul 18 '19 at 8:17
  • @JeremyP Both interpretations are possible; there is no rigorous definition that I know of. But as Raffzahn said, it has a 32-bit operation; the criterion as listed by Martin Rosenau is fulfilled. Of course, by this criterion, you could call a Pentium 4 128-bit, since it allowed 128-bit integer addition/multiplication using XMM registers. Some CPU manufacturers tried that too (remember those 256-bit consoles?). – Luaan Jul 18 '19 at 8:24
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    @Luaan Agreed. In fact Sinclair called the 68008 in the QL an 8/16/32 bit processor. However, at the time, everybody thought of the 68000 as 16 bit except the marketing droids who wanted to make it appear more super. – JeremyP Jul 18 '19 at 9:02
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    "48 bits address width" is about virtual addresses; an actual bus would be physical addresses. The ISA hard limit for x86-64 physical address is 52 bits (page-table-entry format): Why in 64bit the virtual address are 4 bits short (48bit long) compared with the physical address (52 bit long)?. Actual HW implements 40 or so physical address bits, en.wikipedia.org/wiki/RAM_limit#64_bit_computing saying 40 to 52. Future HW will support another level of page tables for another 9 virtual address bits (57 total), allowing lots of NV-DIMM storage. – Peter Cordes Jul 19 '19 at 17:30

An N-bit CPU is generally one which can perform a significant range of individual operations on N-bit values about as quickly as it could perform those operations on anything smaller. There is sometimes a little wiggle room as to what "about as quickly" means, but usually it's pretty clear. Note that while N would often match the size of the ALU, that isn't always the case.

The Z80 has a 4-bit ALU, but it can add two eight-bit values faster than it can add two values of any other size (four cycles for a register-to-accumulator add). It has instructions to add two 16-bit values, but the fastest of those takes almost three times as long (11 cycles) as the instruction to add two 8-bit values. Thus, it is essentially always described as an 8-bit processor.

The CDP1802 has a one-bit ALU, but it the clock pulses eight times for each machine cycle. The CDP has sixteen 16-bit registers, and can increment or decrement two of them (or increment one of them twice) in a two-machine-cycle instruction. Despite the ability to directly increment and decrement any 16-bit register in a single machine cycle, however, and despite its one-bit ALU, it is always described as an 8-bit processor.

The 8088 has a 16-bit ALU, but an 8-bit memory bus. Nearly all operations involving registers can be performed on 16-bit values just as fast as with 8-bit values, but operations which involve reading and writing memory are about 50% slower. Because 16-bit register operations are generally as fast as 8-bit operations, it is often described as a 16-bit CPU, but occasionally as an 8-bit one.

The 68000 has a 16-bit ALU and memory bus. Operations involving 32-bit values are generally about 50% slower than operations involving 16-bit ones. It is thus usually described as a 16-bit CPU, but because most 32-bit operations take significantly less than twice as long as 16-bit ones, it is sometimes described as 32-bit. C compilers for the 68000 often allow int to be configured as either 16 or 32 bits.

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  • This question has gotten several good, succinct answers, but I think this one is the best. – Davislor Jul 19 '19 at 11:14
  • It's also the most fascinating of the answers as the first computer I built was based on the CDP1802 and it explains why there were so many clocks per instruction cycle. I definitely learned something new today! – Julie in Austin Jul 20 '19 at 21:17

There are many great answers here and it seems safe to assume that the given answers have established that bitness is about the data a CPU handles. After all, the task of a CPU is Data Processing not Address Generation.

Next to all relevant criteria have been mentioned, but I'd like to take it a step back to a more generic approach, showing that there are three basic ways bitness can be defined by

  1. Marketing
  2. ISA
  3. Implementation

And it always works in this order.

And the first one is often forgotten(*1) or ignored (*2).


Noteworthy here is that it's not always about more is better - like Atari did by marketing the Jaguar as 64 bit. Motorola for example did originally market the 68k as being 16 bit (and so did many early users). At that time 8 bit CPUs were standard for microcomputers, with the exception of some 16 bit families (PACE et. al.), so 16 bit were seen as the next step. Going as sole 32 bit provider was seen as an uphill battle against every other offering, as customers would rather ask why spend money on something they don't need. So while some of the 16 bit age, like 9900 or 8086 were really 16 bit, Motorola, National and Zilog placed their new development as 16 bit - despite the fact that we today would see them as 32 bit.


Tech people often focus on the lowest level, implementation. What is the size of the data bus, internal or external, the size of the ALU, registers and so on. While this does have impacts on performance and for sure offers a good game of 'mine is better than yours', it is very specific on single implementations, making it hard to see the whole picture - after all, a NS32008 is an 8 bit CPU, thus not better than an 8080, isn't it?

ISA - Instruction Set Architecture

Taking the (abstract) ISA as guideline is eventually not just the middle of the list but also the middle ground here. An ISA describes how a CPU works at instruction level. It describes what the CPU can do using the resources visible to a program handled by the instructions available. It doesn't care if a CPU is implemented bit serial or full parallel or anything inbetween. It doesn't rely on how wide an external bus is either.

ISA vs. Implementation

An ISA can be implemented in a wide variety, and that has been used all over since the early days (of computer families). IBM /360 were not always 32 bit implementations - but they always present the same 32 bit ISA. Or take PDP-8/S, a bit serial implementation of the PDP-8 ISA. And not at least the 68008 vs. 68000 vs. 68020. While having many different bitnesses in terms of register, ALU and bus, they are all the same 32 bit ISA.

In the end, it's the ISA that decides what a CPU is. Implementation differentiates two chips in usage not more than using the same at variations of clock speed. I guess noone will state that a 2 MHz 6502 is a different CPU than a 1 MHz one.

Technology vs. Marketing

(...silence ...)

Last but not least it should be noted that all the bitness arguments are a thing of the past. And even back then not all that meaningful. It was (made) important during a phase of maturing, when going from barely usable architectures and implementations thereof toward today's all around capable ones. So trying to make sense from today's point of view does not always produce a valid result.

*1 - Martin made a great point by the XC2000

*2 - Especially here, as most of us are rather on the technological side than about pumping out funny phrases.

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    That's a really interesting point about m68k being marketed as 16-bit to avoid seeming extravagant and costly vs. its purely 16-bit competitors. I'd never thought of it from that angle. – Peter Cordes Jul 19 '19 at 17:37
  • ISA vs. Implementation: implementation changes can get enshrined in the ISA. For example, Intel's x86 manuals guarantee that a 64-bit aligned load or store is atomic on Pentium and later. Even though it's still a 32-bit CPU! The few 64-bit load or store instructions include x87 fld and fild, and integer cmpxchg8b. (And on Pentium MMX, movq). Since an 80-bit x87 reg has a 64-bit significand, fild m64 ; fistp m64 can atomically copy an arbitrary 64-bit integer without corrupting it (e.g. to a local tmp on the stack for integer reload). GCC does this for stdatomic without SSE. – Peter Cordes Jul 19 '19 at 17:41
  • Why is integer assignment on a naturally aligned variable atomic on x86? quotes the relevant parts of Intel's manuals that give guarantees for P5 Pentium and later. And for P6 and later re: cacheable loads / stores. – Peter Cordes Jul 19 '19 at 17:42
  • There isn't really a complete x86 ISA standard separate from implementations. In the ARM world for example, they might say that ARMv5 adds some new guarantee of something, and these various microarchitectures are implementations of ARMv5. In the x86 world, we have the same thing just documented differently. New generations of uarches add new guarantees. Intel's uncooperative-to-AMD attitude means that there isn't good documentation of portable guarantees; compiler devs have to find the common subset of what Intel and AMD guarantee when implementing __atomic_... support. – Peter Cordes Jul 19 '19 at 20:49
  • Part of what makes something an ISA guarantee is that it's guaranteed to work on all future CPUs. Intel doesn't document things that are just implementation details of a specific uarch. (Other than in their optimization manual for performance effects. Things that matter for correctness are left undocumented if they don't want you to write code that relies on it. Lots of things like that have been reverse-engineered, e.g. page-walk coherence in some cases: blog.stuffedcow.net/2015/08/pagewalk-coherence/.) – Peter Cordes Jul 19 '19 at 20:53

the bitness of a CPU specifies how much memory it can address (which is determined by the size of the CPU's address bus I guess)

Not really. It is generally defined by the size of data it natively operates over, so the size of its registers. The definition is slightly fuzzy though as some CPUs have a range of register sizes for different features, and of course there is marketing involved as others have mentioned.

To give a few examples which should clarify the "it is generally the registers that count", certainly for Intel CPUs and related implementations:

  • The 8086 has 16-bit registers (though can access many of them as 8-bit ones too) and a 16-bit data bus so is generally considered a 16-bit CPU despite the 20-bit address bus. Same for the 80186.
  • The 8088 is basically an 8086 with an 8-bit data bus so can work on cheaper motherboards. Despite the smaller external bus it still deals with 16-bit vales internally (the bus has a shim between it and the rest of the CPU to translate one 16-bit request into two 8-bit ones), so is still considered a 16-bit CPU and can run all the software that the 8086 can.
  • The 80286, still 16-bit like the 8086, had a 24-bit address bus, allowing eays use of 16Mb of memory instead of being limited to 1Mb (without paging tricks like EMS).
  • The 80386 (latterly referred to as the DX once the SX was released) has 32-bit registers (though can use them in 16-bit and 8-bit chunks in many ways) and a 32-bit data bus and a 32-bit address bus. There is little question with this one!
  • The 386SX is to the 386DX what the 8088 is to the 8086: the same internals but reduced external interfaces so it can run on cheaper motherboards. This had 32-bit internals, so is considered a 32-bit CPU, but a 16-bit data bus and 24-bit address bus for talking to the rest of the machine (more like a 286).
  • The 486 had a built-in floating-point co-processor which operates on 80-bit "long double" registers. This does not make the whole chip 80-bit though as these are not general purpose registers: the 486 is 32-bit mostly internally just like the 386 line.
  • The original Pentium CPUs were still 32-bit internally (apart from the floating-point registers) with a 32-bit address bus, so are called 32-bit chips, but had a 64-bit data bus so that memory could be transferred to/from the CPUs internal cache faster (CPU<->RAM bandwidth being a major bottleneck by that point as CPUs sped up much faster than RAM did)
  • Later versions of the Pentium had another little complication: the MMX registers were 64-bit. But like floating-point registers these are not general purpose registers, so they do not make the whole chip be considered 64-bit.
  • Also, many 32-bit Pentiums (PPro, PIII, possible the PII, some Celerons) had 36-bit address busses allowing them to access 64GB or memory instead of being limited to 4GB as the first versions were (unless certain paging tricks like PAE were used).
  • Straying quite far out from "retro computing" now, some of AMD's 64-bit designs used a 40-bit address bus (still 64-bit internals and 64-bit data bus) allowing a Terabyte of address space. Both they and Intel seem to have standardised on a 48-bit address bus.

Non-Intel chips follow very similar conventions. For instance most 8-bit CPUs like the 6502 family had 16-bit address busses (so they could address 64Kb of memory).

It can be a bit confused, and it can get even more complicated when you start moving away from general purpose CPUs to start looking at more specialised processors, but hopefully this makes it a little clearer to you.

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  • Not to mention that later Pentium (Pro until Core2) had more than 32 address lines while still being 32 Bit data. – Raffzahn Jul 18 '19 at 11:00
  • @Raffzahn - I thought I'd made my point by then so stopped, but it probably makes sense to finish the job and mention that. And the 48-bit address bus. I'll edit those in. – David Spillett Jul 18 '19 at 14:33
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    Oh, no doubt, you made a great list. I just remembered that PAE was again an oddity where the CPUs stayed 32 Bit, but addressing went 36 (Pentium Pro) and 38 (Xeon) even before the CPU itself moved to 64 bit - and all of that complete invisible to user level ISA. – Raffzahn Jul 18 '19 at 14:40
  • 48-bit is the x86-64 virtual address width, and it's tied to the page-table format so it has to be standardized (4-level x 9-bit page tables + 12 bit page offset). That's not a bus; translation to physical happens right away in the load/store execution units. The physical address space is up to 52 bits wide (PTE format) Why in 64bit the virtual address are 4 bits short (48bit long) compared with the physical address (52 bit long)?. But physical address width depends on the CPU model, with some as narrow as 40-ish bits. – Peter Cordes Jul 19 '19 at 17:51
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    unless certain paging tricks like PAE were used. Umm, PAE is the trick that allows them to access more than 4GB of physical memory. Virtual / linear addresses are still 32-bit in 32-bit mode; only paging with PAE can generate physical addresses larger than that. – Peter Cordes Jul 19 '19 at 21:01

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