# How does states, bus cycles and clock cycles differ in the M68000?

I'm trying to understand the difference in `bus cycles`, `clock cycles` and `states` within a 68000 processor.

According to the user manual,

``````A bus cycle consists of eight states...
``````

Lets assume the 68K has a CLK signal that is 8 MHz (based on an 8 MHz crystal oscillator attached to the CLK pin). That, I believe, is a "CPU Clock" or just "Clock". It's the fastest clock signal the 68K is aware of.

So each of the two phases of that signal (LOW and HIGH) would be 62.5ns. Both the low and high phase of that clock would be one clock cycle.

Now, referring back to the user manual, a bus cycle would be 8 clock cycles in length. Basically, 16 "ticks" or phase changes of the crystal oscillator.

Next, that bus cycle is broken into 8 states. Each of those states would be two ticks of the crystal oscillator. Which means each state is equivalent to a full cycle of the crystal oscillator. Which would be 62.5ns x 2 in this example.

After reading all of that, is my logic and understanding correct? The user manual seems to toss around bus cycles, clock cycles, etc. and I want to make sure I understand their meanings.

I'm trying to understand the difference in bus cycles,

A bus sycle is one transaction on the processor bus. Roughly one read or write.

clock cycles

A clock cycle is one high and low phase of the clock signal ... well, a cycle.

and states within a 68000 processor.

States are the in general the steps the CPU takes to execute an instruction - here especially about the sequence of signals the CPU outputs or reads during execution.

According to the user manual,

If you got this already, you might as well look at Page 4-2, giving a nice diagram as well as a list of the 8 basic states on p.4-3.

A bus cycle consists of eight states...

Jup

During one clock cycle the CPU goes thru two states - using each edge to trigger one step (*1) One bus cycle needs to go thru 8 states, so it will be 4 clock cycles.

And looking at the 68000 instruction timing you'll see that next to all take multiples of 4 clocks.

Now, referring back to the user manual, a bus cycle would be 8 clock cycles in length. Basically, 16 "ticks" or phase changes of the crystal oscillator.

No, look at the graphics, it's 8 ticks thus 4 cycles.

After reading all of that, is my logic and understanding correct?

Basically yes, except for above skew.

The user manual seems to toss around bus cycles, clock cycles, etc. and I want to make sure I understand their meanings.

Well,

• states are used to show the internal series of events,
• clock cycles to make it easy to refer to the system clock for speed calculation and
• bus cycles to look at the execution from a more abstract perspective, leaving all the dirty bits unmentioned :))

*1 - Much like the 6502, except it uses also a shifted signals to turn the 2 edges into non overlapping clocks.

• Chapter 4 is probably the wrong chapter of the manual. That is the chapter that describes the operation of the 8 bit bus and would be correct for the 68008 but not usually the 68000. Chapter 5 describes the 16 bit bus cycle. Aug 20, 2019 at 8:58
• @JeremyP Well, I guess both may work as well, as the difference is just the validity of D8..D15. Regarding the bus cycles, the question refers to, they are the same - or am I missing something? (Can't look up right now). Aug 21, 2019 at 13:19
• @JeremyP Raffzahn is correct: The 8-bit read/write cycles described in chapter 4 and the 16-bit read/write cycles described in chapter 5 are the same, with the exception that A0 is used and U̅D̅S̅ (if it exists on that model of CPU) being high and only L̅D̅S̅ or D̅S̅ being low. But I agree it might be less confusing to reference section 5 instead. (And maybe to remove all the quoting of the question; this isn't a mailing list where people might not have the original question handy.)
– cjs
Aug 24, 2019 at 11:08

That's correct in that example.

A state is any constant (after settling) bus state. When the 68000 changes state, it does so on a clock transition.

A clock cycle is one complete cycle of the clock. For an 8Mhz 68000, there are 8,000,000 clock cycles per second.

A bus cycle is the complete set of states that describes a bus interaction — most normally a read or write, and usually 4 cycles / 8 states long.

However it is not true that all bus cycles are 4 clock cycles long, e.g. TAS to memory is intended for multiprocessor mutual exclusion, so it uses an atomic read-modify-write bus cycle of 10 clock cycles.

It is also not true that every clock cycle contains two states. When performing operations like DIV[U/S] the 68000 will do a lot of internal processing before getting to its next bus interaction, signalling nothing* in the interim.

*) other than changes to E, the divide-by-10 clock it outputs for 6800-style peripherals.

• @Raffzahn clock cycles, definitely. Corrected. Thanks! Jul 24, 2019 at 16:26
• Also, TAS is the exception to the rule as only RMW - AFAIR. Further there are of course states inbetween two cycles. Each and every clock cycle has two states. Just because no signal changes dosn't make that basic operation structure go away. Jul 24, 2019 at 18:26
• Right; I think even DTACK and co are checked once a clock cycle, so you can't end up out of phase in that sense; and further to underscore your point, a predecrement costs two clock cycles and can't always be overlapped with useful work. Jul 24, 2019 at 19:28
• You might mention that even a standard read cycle (or any other) can be more than 4 clock cycles long if wait states are inserted. Fire 5-3 gives examples of two reads, one without wait states (4 clock cycles) and one with two wait states (6 clock cycles).
– cjs
Aug 24, 2019 at 11:12