A quote from the Wikipedia:

The PDP-5's instruction set was later expanded in its successor, the PDP-8, to handle more bit rotations and to increase the maximum memory size from 4K words to 32K words.

The part about the increase in max memory size I believe is false, since that's done by optional external hardware, the Memory Extension Controller which presumably may equally well augment the PDP-5.

And the part about handling more bit rotations, I also cannot see how the PDP-5's Group 1 OPR is any different from that of the PDP-8.

So is the PDP-8 really any different from the -5?

3 Answers 3


There is a section in the DEC FAQ that describes the differences between the PDP-5 and PDP-8 instruction set:

Compatability: The core of the PDP-8 instruction set is present, but memory location zero is the program counter, and interrupts are handled differently. The Group 1 OPR rotate instructions cannot be combined with IAC or CMA; this limits the ability of the PDP-5 to support code from later models.

This makes much more sense than "handle[s] more bit rotations" (can someone update the Wikipedia article?). Combining CLA CLC with IAC and/or CMA plus a rotate operation is useful to quickly load constants into AC.

Other differences:

The machine does not support 3 cycle data-break (DMA transfers using memory to hold buffer address and word-count information), so many later PDP-8 peripherals cannot be used on the PDP-5. In addition, DMA transfers are not allowed outside the program's current 4K data field, severely limiting software compatability on systems with over 4K of memory where either interrupts or software initiated changes to the data field during a transfer would cause chaos.

But of course the main reason to prefer the PDP-8 over the PDP-5 was performance and price.


The PDP-5 also offered expansion up to 32K words, similar to the PDP-8. This was the "Memory Extension Control Type 154" as seen on the second-last page of this PDP-5 brochure:

TYPE 154
Allows expansion of the PDP-5 memory from 4096
to 32,768 words in increments of 4096 words. Can
be attached to any PDP-5 without requiring changes
to the processor.

So the claim that only the PDP-8 had the "expanded instruction set" for this is wrong. The claim that memory expansion required an expanded instruction set doesn't strike me as utterly unreasonable, since IIRC instruction decoding for additional "IOT" instructions was on the cards that added the peripheral, so you could argue that the particular IOT (sub-?)instruction didn't exist in the machine until the peripheral was added.

Regarding rotations, as well as the standard four (accumulator and link left/right 1/2 positions) shared by the PDP-5 and PDP-8 in operate group 1, DEC's 1974 PDP-8 Pocket Reference Card includes a section called "combined operate microinstructions" that includes among other things two shifts and two additional rotates:

CLL RAR  7110  shift positive number one right     1,4
CLL RAL  7104  shift positive number one left      1,4
CLL RTL  7106  clear link, rotate 2 left           1,4
CLL RTR  7112  clear link, rotate 2 right          1,4

It's not clear to me if these rotate through the link or just rotate the accumulator. If the former, they're not different in how much gets rotated, but they are different in that they change the data before rotation.

These don't seem to be documented in various other instruction set summaries, so I'm wondering if these were instructions added by optional hardware, rather than part of the base PDP-8.

  • 4
    The combined operations are just combinations, so they are not explicitely mentioned everywhere, because you can derive them from the other operations. Yes, they rotate through the link.
    – dirkt
    Commented Jul 25, 2019 at 16:43

The following information is incorrect, but preserved for future notice

The most important difference is that PDP-5 doesn't have "Zero Page Addressing" as on PDP-8

PDP-5's instruction format:

  1. Op-code: 3 bits
  2. Indirect: 1 bit
  3. In-Page Address: 8 bits

PDP-8's instruction format:

  1. Op-code: 3 bits
  2. Indirect: 1 bit
  3. Zero Page: 1 bit
  4. In-Page Address: 7 bits
  • 2
    This is incorrect. The page address structures of the PDP-5 and all members of the PDP-8 family are identical. Commented Aug 24, 2019 at 4:38
  • 1
    The PROGRAMMED DATA PROCESSOR-5 HANDBOOK (Digital Equipment Corporation, 1964) gordonbell.azurewebsites.net/digital/… describes the page address structure of the PDP-5 on page 12, with diagram on page 13. Commented Aug 24, 2019 at 4:50
  • 2
    Do not use the information in the PROGRAMMED DATA PROCESSOR-5 sales brochure (F-51, Digital Equipment Corporation, March 1964) s3data.computerhistory.org/brochures/… It was written by someone who did not understand the page address structure, and was never intended to be used as a programming guide. Commented Aug 24, 2019 at 4:51
  • 1
    @A.I.Breveleri The brochure's not incorrect, though neither clear nor complete. The diagram on p. 7 shows bits 4-11 as the address field of the instruction word, and bit 4 is marked "Memory Page." The text says, "The memory page bit of the instruction word refers to the organization of the computer memory in 128 (2008)-word 'pages.' For direct addressing, the programmer uses bits 4 through 11 to select one of 256 memory locations." That's correct as far as it goes, even though it doesn't explain that this is one of 128 locations in the zero page or current page depending on the value of bit 4.
    – cjs
    Commented Aug 24, 2019 at 13:27
  • 1
    I didn't say the information in the brochure is incorrect. I said don't use it. Commented Aug 27, 2019 at 11:48

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