As I understand it, the Intel 8088 CPU used in the original IBM PC had two interrupt lines: INTR and NMI. INTR was fed from the Intel 8259 Programmable Interrupt Controller, which handled the IRQs from the rest of the system (and presented the interrupt number on lines AD0-AD7 for the CPU to read). What, if anything, was the NMI line connected to? What did BIOS/DOS do when interrupt 2 arrived? Were there any differences in this regard between the PC, XT, or AT?
In a 100% compatible PC, NMI is used only to communicate unrecoverable errors — normally a RAM parity failure, but possibly something else, which should reveal itself via one of the system control ports, specifically you should check:
- b4: watchdog timer status;
- b6: channel check failure (i.e. a bus failure, likely a peripheral device);
- b7: parity check failure.
As indicated by e.g. this description of the Phoenix BIOS, possible NMI sources are
- Memory parity errors
- x87 Coprocessor errors
- I/O card NMI (for whatever reason the I/O card decides to invoke it)
- DMA bus time-out errors (AT only)
Additionally, the Programmable Interrupt Timer (PIT; 8253 or 8254) could generate an NMI using a watchdog and possibly also on user (programmer) request.
At least the Phoenix BIOS just displayed the error, and then the system must be rebooted (warm boot via Ctrl-Alt-Del was allowed).
There seems to be some additional logic regarding Coprocessor errors.
On the IBM PCJr, the NMI was used by the keyboard device to signal the CPU.
(Source: “The Peter Norton Programmer’s Guide to the IBM PC”, chapter 3, under “Changing Interrupt Vectors” while discussing CLI)
The original IBM 5150 Personal Computer (the IBM PC) connected the Non-Maskable Interrupt to the I/O Check signal, which could be driven by an add-in card, or by the on-board memory. If the systems memory detected a parity error, it would trigger a NMI, and the systems software would halt the machine and display an on screen error. You can read about this in the IBM PC Technical Reference Manual.
IBM decided to do this because in a business setting they felt it was better to crash than to provide an incorrect computational result. Imagine if a payroll run added $32768.00 to someones paycheck due to a single-bit flip.
Modern PC systems still use NMI as a response to PCIe errors. However consumer grade computers no longer have parity protected DRAM, and server grade systems use ECC that no only detects, but corrects errors. These errors are reported though a new mechanism called the Machine Check Architecture.
Funny story... years ago Microsoft engineers discovered they could deliberately blue screen windows by shorting out the A1/B1 pins (IO Check and GND) on a computers ISA slot. This was a helpful debug aid when needing to halt a hung computer (the blue screen activated the windows kernel debugger). When the ISA slot was replaced with PCI, some manufactures added a special button to trigger an NMI so that this debug 'hack' would not be lost.