As I understand it, the Intel 8088 CPU used in the original IBM PC had two interrupt lines: INTR and NMI. INTR was fed from the Intel 8259 Programmable Interrupt Controller, which handled the IRQs from the rest of the system (and presented the interrupt number on lines AD0-AD7 for the CPU to read). What, if anything, was the NMI line connected to? What did BIOS/DOS do when interrupt 2 arrived? Were there any differences in this regard between the PC, XT, or AT?
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4 Answers
In a 100% compatible PC, NMI is used only to communicate unrecoverable errors — normally a RAM parity failure, but possibly something else, which should reveal itself via one of the system control ports. Specifically you should check:
Port A:
- b4: watchdog timer status;
Port B:
- b6: channel check failure (i.e. a bus failure, likely a peripheral device);
- b7: parity check failure.
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3I didn't realize the PC kept track of memory parity! I would've thought, given the size constraints of the era, that every transistor in the memory would've gone toward usable space and not error detection.– smitelliCommented Jul 27, 2019 at 2:47
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4@smitelli: Bit rot was a fact of life back then. The fix turned out to be making memory smaller.– JoshuaCommented Jul 27, 2019 at 14:17
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4@Joshua: From what I read, the fix turned out to be using materials that weren't slightly radioactive.– supercatCommented Jul 27, 2019 at 22:54
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8Not all clones did but the real IBM PC had a parity bit. That was no different to many pre-IBM PC machines.– Alan CoxCommented Jul 27, 2019 at 22:58
As indicated by e.g. this description of the Phoenix BIOS, possible NMI sources are
- Memory parity errors
- x87 Coprocessor errors
- I/O card NMI (for whatever reason the I/O card decides to invoke it)
- DMA bus time-out errors (AT only)
Additionally, the Programmable Interrupt Timer (PIT; 8253 or 8254) could generate an NMI using a watchdog and possibly also on user (programmer) request.
At least the Phoenix BIOS just displayed the error, and then the system must be rebooted (warm boot via Ctrl-Alt-Del was allowed).
There seems to be some additional logic regarding Coprocessor errors.
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4In the mid-80s I worked on a real-time data acquisition controller that used NMI to signal that data was ready. I also recently threw away a PC card that had two traces and a button, allowing you to use NMI to enter a debugger. Commented Jul 27, 2019 at 10:38
On the IBM PCJr, the NMI was used by the keyboard device to signal the CPU.
(Source: “The Peter Norton Programmer’s Guide to the IBM PC”, chapter 3, under “Changing Interrupt Vectors” while discussing CLI)
answered Jul 27, 2019 at 3:15
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2I've had a glance in my copy of the later "P.N. guide to the PC and PS/2", and found nothing. But the PCjr Technical Reference describes the infrared keyboard interface generating NMIs on page 2-99: archive.org/details/IbmPcjrTechnicalReference/page/n123– KazCommented Jul 27, 2019 at 6:30
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@kaz, thanks for checking and finding an authoritative source; I have never owned later editions of the P.N. Book. By the time PS/2 came out, the PCJr had been out of the market for a while and all PCJr information might have been purged from the book. In fact from online sources I found, the introduction implies they purged not just the PCJr but also the XT and the PC Convertible. And the text I used as a source (under “Changing Interrupt Vectors” while discussing the use of CLI) was changed from the original and no longer mentions the PCJr. Commented Jul 27, 2019 at 11:06
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1I don't know what Norton's book might have said on the subject, but I bought a PCjr as my first PC when IBM was having a fire sale to get rid of those turkeys and I never had a problem with the keyboard causing disk read problems. But then, I never used the stupid infrared-link keyboard - I bought an aftermarket keyboard that plugged directly into a port on the back of the machine, like God intended! :-) Commented Jul 28, 2019 at 21:05
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Also used a PCjr extensively back in the day. Never noticed any issues with activity / NMI crashes. Used infrared and corded keyboards at various point. Commented Jul 30, 2019 at 19:50
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1I’ve removed the paragraph about timing issues because I don’t have a source and it is clearly disputed by folks with direct experience. I must have misremembered. Thank you. Commented Jul 30, 2019 at 20:39
The original IBM 5150 Personal Computer (the IBM PC) connected the Non-Maskable Interrupt to the I/O Check signal, which could be driven by an add-in card, or by the on-board memory. If the systems memory detected a parity error, it would trigger a NMI, and the systems software would halt the machine and display an on screen error. You can read about this in the IBM PC Technical Reference Manual.
IBM decided to do this because in a business setting they felt it was better to crash than to provide an incorrect computational result. Imagine if a payroll run added $32768.00 to someones paycheck due to a single-bit flip.
Modern PC systems still use NMI as a response to PCIe errors. However consumer grade computers no longer have parity protected DRAM, and server grade systems use ECC that no only detects, but corrects errors. These errors are reported though a new mechanism called the Machine Check Architecture.
Funny story... years ago Microsoft engineers discovered they could deliberately blue screen windows by shorting out the A1/B1 pins (IO Check and GND) on a computers ISA slot. This was a helpful debug aid when needing to halt a hung computer (the blue screen activated the windows kernel debugger). When the ISA slot was replaced with PCI, some manufactures added a special button to trigger an NMI so that this debug 'hack' would not be lost.
