As already discussed, the 8086's memory addressing is a little... weird.
The hardware addressing was 20-bit and bytewise, which gives you the 220 addressable bytes (1 MiB).
To the software side, this was exposed as a segment (later, when the 80286 introduced protected mode, renamed a selector, but by default in real mode selectors were set up to work identically to segments) and an offset.
The physical address was generated by taking the segment, left-shifted by four bits (not multiplied by four, as another answer claims), and then adding the offset, then taking the lowest (most significant) 20 bits of the result.
It follows that any given physical memory address can be accessed via a number of different segment:offset pairs. There is no difference to the CPU-RAM interface between, say, F000:FFF0 and FFFF:0. (We can see this as F000<<4 becomes F0000, add FFF0 gives FFFF0; likewise, FFFF<<4 is FFFF0, add 0 gives FFFF0.)
As a consequence, it also follows that segments can overlap. In the above example, segments F000h and FFFFh overlap at address FFFF0h. In general, every segment selects a sliding 64 KiB window of the 1 MiB address space, shifted 16 bytes for each segment.
Memory models are a distraction, here; they mostly influence which segment value is the default for a particular type of operation, and which type of addressing is normally used.
To access a particular physical address, generally speaking, an appropriate segment register is loaded with the correct segment, and then a normal segment:offset access is performed via that segment register. Some instructions (such as jumps) can or even require the programmer to bypass the segment load operation and specify the segment directly in the instruction; other instructions can use only a specific segment register.
Since loading a segment register is a relatively invasive operation (as it changes global CPU state which you'll potentially need to reset before doing something else), it's something you'd try to avoid. By carefully choosing how you're addressing memory, many segment changes could be avoided, or restricted to the extra segment register, ES.
The CPU doesn't care about the type of segment (on the 8086/8088, there is nothing to mark a stack segment as different from a code or data segment; features like NX, or read-only segments, came later), but some operations have restrictions on which segment registers they can be used with. For example, you cannot perform an intersegment jump instruction into code pointed at by DS, but that's a restriction of the jump instruction, not the CPU. If for some strange reason you really want to jump to DS:IP+4, you just need to put that address in a place where a jump instruction can use it; there is no need to do anything to the memory itself.
Back in the day, the ability of the 8086/8088 to provide these different windows into the address space was sold as a feature by Intel, proposing that it would ease the development of multitasking or multiuser environments. For example, from the iAPX 86/88 user's manual, page 2-11:
The segmented structure of the 8086/8088
memory space supports modular software design
by discouraging huge, monolithic programs. The
segments also can be used to advantage in many
programming situations. Take, for example, the
case of an editor for several on-line terminals. A
64k text buffer (probably an extra segment) could
be assigned to each terminal. A single program
could maintain all the buffers by simply changing
register ES to point to the buffer of the terminal