The first mention of SPI that I can find is in the Motorola data book
Single-chip Microcomputer Data from 1984.¹
The three devices in that book that support "Serial Peripheral
Interface" are the 6505K2/K3, 6505S2 and 68HC11A4. The data sheets for
all of these are marked "This document contains information on a
product under development. Motorola reserves the right to change or
discontinue this product without notice." Contrasting this with
"This document contains information on a new product" or no notice
at all on other data sheets, I conjecture that these devices were not
available for some time after the book had been printed, but the
descriptions themselves make it clear that this is when SPI had been
invented. (Nothing like it appears in the 1981 data book).
The 6805K2/K3 (227/275) data sheet and 6805S2 (390/438) description
label the SPI interface pins differently from what eventually became
SPIS (slave select, still active low, despite no
SPICL (clock), and two pins both labeled
which correspond to
MOSI. (I guess at the time of writing
they'd not figured out how to clearly separate the two, since they
both do both input and output, depending on role.) The 68HC11A4 data
sheet (599/647), however, uses the now-standard
The 6505K2/K3 data sheet gives no information on SPI, other than to
say that it's there.
The 68HC11A4 data sheet, which describes it on the first page as "A
New Serial Peripheral Interface" (emph. mine), provides little more:
just a half page of text containing a brief description and a
paragraph on each pin. (613/661) But the two sample system
configurations they give (figure 5) are quite interesting. The first
is a "Master-slave system configuration" consisting of five MC68HC11A4
MCUs, one master and four slaves. The second is the same hardware in a
multi-master configuration (three master/slave, two slave).
The 6805S2 description, however, really gets into the details,
providing an entire 25 page section on SPI (415/463) which describes
not only the hardware but how to use it in many different ways.² Much
of it, the majority in fact, discusses how to deal with bus
arbitration using the clock line, the data line, a common select line
or combinations of these. There's also discussion of addressing
devices via addresses in the messages, rather than using select lines
The example configuration in figure 4-15 (438/486) shows a three-wire
daisy-chain configuration with slaves "MCU 1", "MCU 2" and
"Peripheral" and master device "MCU 3." These all share a common slave
select line with a pull-up resistor to Vcc. As the text mentions, all
devices must understand some sort of protocol within the data stream
to determine if messages are addressed to them, they should change the
direction of information flow, and so on.
The example configuration in figure 4-16 (439/487) is three MCUs in a
bus configuration, again sharing a common slave select line with a
pull-up resistor to Vcc. This could be multi-master using any of a
variety of arbitration methods described in the text.
All this attention paid to multiple masters, bus arbitration,
suggestions of addressing in packets and so on makes me disagree with
the the other answers here that suggest this was designed primarily as
a simple way to talk to 74xxx shift registers and the like. The
ability to do that as well was clearly something they had in mind (the
68HC11A4 data sheet mentions that it provides both "Interface With Low
Cost 'Dumb' Peripherals" and "Interface With Intelligent Peripherals
on Master/Slave Basis" (613/661)) since with some minimal design work
it comes "for free," but the massive amount of work put into desiging
for and describing bus arbitration and the multiple examples of
multi-MCU systems, including multi-master multi-MCU systems, makes it
clear that the intent was to provide a lot more.
As well demonstrating use of the SPI interface be used for MCU-MCU
communication, Motorola had at least two peripherals in this catalogue
explicitly claiming to use an SPI interface:
- MC68HC68A1: Serial 10-bit analog-to-digital converter.
"Interface to the A/D converter is through a standard serial
peripheral interface (SPI) unit." (623/671) This appears to use a
two-way communication protocol with configuration commands sent to
the chip and results and samples sent back to the controller, but
the exact protocol isn't documented here.
- MC68HC68R1/2: 8-bit serial static RAMs. "Directly compatible
with SPI interface." (624/672) And address/control byte followed by
data bytes are sent to the RAM and (on reads) it sends back data
¹ Except where noted otherwise, page references here are to this book
in the form "(nnn/mmm)" where nnn is the page number from
section 3 and mmm is the page of the PDF document: "(227/275)" is
page 3-227 in the book and page 275 of the PDF.
² Interestingly, the 6805S2 offers some extra capabilities in the SPI
hardware let it (with a bit of software support) do one-wire operation
without a clock line. (435/483) This is claimed to allow you to use
the SPI hardware to communicate with the ACIA built-in to the 6801.
This did not appear in later 68HC11 data sheets I've looked at.
There's also discussion of configurations that today would not be
considered "SPI," such as single-line half-duplex data