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So far I've figured out that means something about the ram bit I haven't been able to figure out what the problem is

Edit: video link

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    Base 64K RAM failure. Try a different memory stick in the lowest memory slot. – Mick Aug 5 at 20:30
  • @Mick Already tried that :/ – yanagibashi Aug 5 at 20:32
  • Does the motherboard look OK? – wizzwizz4 Aug 5 at 20:41
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Here is a reference to BIOS beep codes. For American Megatrends, look under AMI. 3 beeps means the low 64K failed - a very basic test - which probably means the RAM isn't working at all.

You should first check whether the RAM is compatible with your machine. At that time, there was a lot of variation - 5V vs 3.3V, 30-pin vs 72-pin, EDO vs FPM, not to mention response latency grades from 60ns to 150ns. Usually 70ns FPM will work in a 486.

Watching the first few seconds of video I see you have quite an early board with 30-pin SIMMs, which each provide 8 bits width to the data bus. Since the 486 is a 32-bit bus CPU (unlike the 386 it was never made in a 16-bit bus variant), you always need 4 identical SIMMs together. If you had a board that took 72-pin SIMMs, which have 32-bit width each, you'd be able to try just one like you are.

The effect of fitting just one SIMM in this machine would be to provide storage only at one out of every four bytes in sequence. Software just isn't written to cope with that on the PC.

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    Thanks, that did the trick. One a sidenote, is there a way to tell who manufactured this board there isn't any indications on the board – yanagibashi Aug 5 at 21:02
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    The most reliable reference will be the FCC certification ID, which should be printed on the board somewhere. You can look that up in the FCC's database. – Chromatix Aug 5 at 21:04
  • @yanagibashi MB ID is usually printed on a sticker placed on the lowest PCI or ISA slot (closest to the edge of MB). In some cases its not visible without side view (by using mirror or by removing the MB from case) – Spektre Aug 5 at 22:48
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    The 80486 allows cycles to be completed as 8-bit or 16-bit cycles. It starts a new cycle to request the missing data. But even if the cycle is completed as 8-bit cycle, the data lines of that 8-bit piece of a 32-bit transfer have to be used. I.e. if the 486 reads the DWORD at address 0, you can deliver bytes 0 and 1 on D0-D15 and terminate that cycle as 16-bit cycle. In the next cycle, you need to deliver bytes 2 and 3 on D16-D31. The 80386 is supposed to manage by swapping internally. The 80486 datasheet has a suggested external logic circuit for that. – Michael Karcher Aug 21 at 10:37
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    @MichaelKarcher Not having read that documentation, I expect it would be legal to deliver the data on both halves or all bytes of the bus on reads, and let the CPU choose which one it wanted. You'd still need to separate them on writes to prevent bit collisions, probably using bus transceivers. At any rate, it requires a m/board explicitly designed down to that style of bus, which a typical i486 m/board would not do for the primary RAM slots. – Chromatix Aug 21 at 17:13

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