Additional information to complement the answer by Fuzzy_Bunnys:
1) An Forth chip I like very much is the J1. It even comes with the Verilog source.
It runs e.g. on an Xilinx Spartan 3E FPGA at 80 MHz, and is used for a real-word application (a Ethernet camera). It has a high code density, but a very simple "unencoded" instruction format (even simpler than the Novix NC4000 format).
Though it targets an FPGA, you could probably implement it with discrete chips with a bit of fiddling. But even for a Hobbyists, today's FPGA chips are not that hard to use.
It makes very clever use of the dual-port RAM on the chip; and the (custom) data and return stack is also dual-port.
2) You were asking about the Sh-Boom.
The company Patriot, which acquired the patent for the Sh-Boom, rebranded and reworked the Sh-Boom as the PSC1000 and targeted it to the Java market.
While I don't know any resource for the Sh-Boom itself, there is documentation for the PSC 1000 to at least get a good idea about the structure (even though the documenation only mentions Java, and not Forth, and it's not clear how much has changed from the Sh-Boom).
But you can clearly see the original 16 general purpose registers of the Sh-Boom, an additional Local-Register stack that might have been the return stack on the Sh-Boom, the Operand stack which would have been the data stack, and the overall instruction format which probably hasn't changed much (though details of the instructions might have).
Though it doesn't look simple enough I'd use it to base any hobbyist project on, the J1 architecture looks much better suited to that.