The Amiga custom chip set, in its ECS and AGA versions, seems to contain some registers for what is called an "Ultra-HighRes/DUAL" mode:
DFF078 SPRHDAT W Ext. logic UHRES sprite pointer and data identifier DFF07A BPLHDAT W Ext. logic UHRES bit plane identifier DFF1D0 SPRHSTRT W UHRES sprite vertical start DFF1D2 SPRHSTOP W UHRES sprite vertical stop DFF1D4 BPLHSTRT W UHRES bit plane vertical start DFF1D6 BPLHSTOP W UHRES bit plane vertical stop DFF1D8 HHPOSW W DUAL mode hires H beam counter write DFF1DA HHPOSR R DUAL mode hires H beam counter read DFF1DC BEAMCON0 W Beam counter control register (SHRES,UHRES,PAL) DFF1E6 BPLHMOD W UHRES bit plane modulo DFF1E8 SPRHPTH W UHRES sprite pointer (high 5 bits) DFF1EA SPRHPTL W UHRES sprite pointer (low 15 bits) DFF1EC BPLHPTH W VRam (UHRES) bitplane pointer (hi 5 bits) DFF1EE BPLHPTL W VRam (UHRES) bitplane pointer (lo 15 bits)
(list taken from this page: http://amiga-dev.wikidot.com/information:hardware )
I do remember that ECS added Super-HighRes mode (pixel duration of 35ns as opposed to the 70ns for HighRes and 140ns for Lowres), but I don't remember any mention of other modes, and, at least for the ECS chipset, I remember that using SuperHighRes mode already put quite a strain on my A500 Plus.
Notably, some of the registers's descriptions mention "VRam", that is Video RAM (a kind of RAM that is double port, one of which is usually a serial high-speed port to fetch an entire row of bits). VRam were never supported on classic Amigas and indeed they were supposed to be used only in the never completed AAA chipset (Andrea, Linda, Monica, Mary).
BEAMCOM0 register also contains many flags related to this DUAL/Ultra-HighRes mode, and in one case a register description seems to imply that DAUL mode may actually be meant to allow using two displays (so DUAL is different from Ultra-HighRes?)
What is all of this? What is Ultra-HighRes, what is the DUAL mode? Are they the same mode or two different modes?
Is the Ultra-HighRes mode related to Hedley (aka Commodore A2024 monitor) mode?See Valentino Milazzo's answer below, plus, the A2024 also works under OCS so it clearly isn't connected.
What is the allegedly external circuitry that would have been needed to interface with VRam chips? What is its purpose? Is it just interface logic or does it do something more?
In the case of ECS, which does not have Fast Page Mode and 32 bit data access mode, does the chipset have enough bandwidth available to handle mode that supposedly - by its name - would move even more (twice?) the pixel of Super-HighRes?
Can someone come up with an hypothesis of the timings (pixel clock/period, horizontal clock) and resolution this mode would have provided, from the registers' descriptions in the URL above?
Addendum: the internal memo describing the AAA chipset says:
AAA is designed to be largely register compatible with the ECS chip set. Most of the RGA registers from ECS are supported. The ECS “Ultra hires” registers have been eliminated, as they were never supported in actual practice. Some other display-generation details of ECS are no longer required or supported in AAA.
So it looks like this feature has ben around since ECS.