The Amiga custom chip set, in its ECS and AGA versions, seems to contain some registers for what is called an "Ultra-HighRes/DUAL" mode:

DFF078  SPRHDAT     W   Ext. logic UHRES sprite pointer and data identifier
DFF07A  BPLHDAT     W   Ext. logic UHRES bit plane identifier
DFF1D0  SPRHSTRT    W   UHRES sprite vertical start
DFF1D2  SPRHSTOP    W   UHRES sprite vertical stop
DFF1D4  BPLHSTRT    W   UHRES bit plane vertical start
DFF1D6  BPLHSTOP    W   UHRES bit plane vertical stop
DFF1D8  HHPOSW      W   DUAL mode hires H beam counter write
DFF1DA  HHPOSR      R   DUAL mode hires H beam counter read
DFF1DC  BEAMCON0    W   Beam counter control register (SHRES,UHRES,PAL)
DFF1E6  BPLHMOD     W   UHRES bit plane modulo
DFF1E8  SPRHPTH     W   UHRES sprite pointer (high 5 bits)
DFF1EA  SPRHPTL     W   UHRES sprite pointer (low 15 bits)
DFF1EC  BPLHPTH     W   VRam (UHRES) bitplane pointer (hi 5 bits)
DFF1EE  BPLHPTL     W   VRam (UHRES) bitplane pointer (lo 15 bits)

(list taken from this page: http://amiga-dev.wikidot.com/information:hardware )

I do remember that ECS added Super-HighRes mode (pixel duration of 35ns as opposed to the 70ns for HighRes and 140ns for Lowres), but I don't remember any mention of other modes, and, at least for the ECS chipset, I remember that using SuperHighRes mode already put quite a strain on my A500 Plus.

Notably, some of the registers's descriptions mention "VRam", that is Video RAM (a kind of RAM that is double port, one of which is usually a serial high-speed port to fetch an entire row of bits). VRam were never supported on classic Amigas and indeed they were supposed to be used only in the never completed AAA chipset (Andrea, Linda, Monica, Mary).

The BEAMCOM0 register also contains many flags related to this DUAL/Ultra-HighRes mode, and in one case a register description seems to imply that DAUL mode may actually be meant to allow using two displays (so DUAL is different from Ultra-HighRes?)


  • What is all of this? What is Ultra-HighRes, what is the DUAL mode? Are they the same mode or two different modes?

  • Is the Ultra-HighRes mode related to Hedley (aka Commodore A2024 monitor) mode? See Valentino Milazzo's answer below, plus, the A2024 also works under OCS so it clearly isn't connected.

  • What is the allegedly external circuitry that would have been needed to interface with VRam chips? What is its purpose? Is it just interface logic or does it do something more?

  • In the case of ECS, which does not have Fast Page Mode and 32 bit data access mode, does the chipset have enough bandwidth available to handle mode that supposedly - by its name - would move even more (twice?) the pixel of Super-HighRes?

  • Can someone come up with an hypothesis of the timings (pixel clock/period, horizontal clock) and resolution this mode would have provided, from the registers' descriptions in the URL above?

Addendum: the internal memo describing the AAA chipset says:

AAA is designed to be largely register compatible with the ECS chip set. Most of the RGA registers from ECS are supported. The ECS “Ultra hires” registers have been eliminated, as they were never supported in actual practice. Some other display-generation details of ECS are no longer required or supported in AAA.

So it looks like this feature has ben around since ECS.


I think the idea behind UHRES was to have VRAM connected to an indipendent DAC/CLUT.

The VRAM has a second data port where it outputs the content of a row. This output was connected to the DAC.

Agnus had the responsibility to configure the second data port at each scanline. For this reason, it emits, at the 2nd cycle, on the RGA bus a 078 (BPLHDAT) and on the address bus the content of BPLHPT*.

Some external circuitry monitors the RGA bus and when detects the 078 value, it samples the address bus and uses it to configure the VRAM.

Same happens for the single UHRES Sprite.

DUAL seems related to having two video signals generated at the same time. One by Denise and one by the VRAM DAC. Since the VRAM display had arguably more lines than the Denise's one there was the need to generate more VRAM scanlines for each Denise scanlines.

This is not related to the 2024 which had an internal frame buffer filled by sampling the Amiga digital video output across 4 frames.

As explained this mode didn't use the Amiga chip ram address bus or the RGA bus to fetch the pixels. This was done through the VRAM second port. The chip ram address bus or the RGA bus were needed only few cycles per scanlines just to configure the VRAM. No need for page mode or 32 bit bus.

The vertical resolution is dependent from how the timers were configured. The horizontal resolution from the VRAM timing. Since this external circuitry was never been documented it is hard to know this horizontal resolution.

  • Accepting this question so far, as it is the same conclusion I reached in the past two days by re-reading the register descriptions in the document I linked. That said, does anybody with a logic analyzer want to analyze what happens on the RGA bus when UHRES mode is enabled ? :-D – user180940 Aug 17 at 8:18
  • I updated my old question at retrocomputing.stackexchange.com/questions/2706/… to propose that ECS and/or AGA may indeed be the implementation of Jay Miner's "Ranger" chipset. – user180940 Aug 17 at 9:51

The ECS chipset appears to have had support for a new UHRES mode added, but it was never completed. It seems to be related to the Ranger chipset developed by Jay Miner.

The idea seems to have been to move display fetch off Agnus to a separate chip with its own VRAM, which was never completed. That would allow greater bandwidth to video memory, one of the major limitations of the Amiga architecture.

It seems that Agnus would still generate video timing and perhaps even addresses for video fetch, but the actual fetch cycles would be done by a different chip. Perhaps the DUAL mode referenced would allow OCS Amiga modes to be combined with this new mode. It's not clear how the blitter and copper would have interacted with it, if at all.

In principal it's a good idea. The Amiga OCS chipset suffers from a limited amount of memory bandwith available for the CPU, screen refresh, copper, audio, blitter, disk DMA and more to all use. A separate dedicated VRAM with its own bus would have freed up a huge number of cycles for the CPU, and could have potentially offered high resolutions and large numbers of sprites or a very fast blitter.

In the end it seemed that VRAM was too expensive and the idea was dropped by Commodore, releasing the ECS chipset with the registers and probably some of the necessary hardware implemented but without the extra chip or VRAM.

  • Uhm, I believe you're wrong. The additional 2 bits needed for the bitplane pointers to address 2MB instead of 512KB in ECS Agnus are added to the "high" bitplane pointers, the same as in the original ECS. The total horizontal line length in color clocks is 244 clocks of 280ns (which makes the 15.75kHz horizontal frequency for the 525/625 lines TV standard), and that's specified in register HTOTAL (also new for ECS). DUAL cannot refer to dual-playfield, that's available in OCS too, while this DUAL flag is enabled in ECS specific BEAMCON0. – user180940 Aug 14 at 16:14

I think you are not taking into account both of the new video modes supported by the Amiga ECS chipset using the higher dot clock:

  1. Super-Hires Mode: 1280 pixel horizontal resolution, interlaced or non-interlaced lines, with a 15.7 kHz horizontal frequency.
  2. Productivity Mode: 640 pixel horizontal resolution (same as Hires), 480 lines, with a 31 kHz horizontal frequency.

Because of the different scan mode/# of lines for Productivity Mode, additional "DUAL" registers were needed to fully support this mode. The UHRES registers just applied to the higher dot clock; thus, they worked for either Super-Hires or Productivity.

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