I know that the 486SX had its FPU disabled, maybe by binning 486 CPUs into those with and without functioning FPUs. But did Intel eventually make a 486SX revision without an FPU on the die?

  • @JonCuster those were still the days of mostly-manual layout for Intel so a "design rules tweak" was not easy. And shrinks back then sometimes did not change the layout (indeed, it was of great value to be able to keep the manual layouts). Obviously some areas like the cache were auto generated and even the random logic may be automated within function blocks but the floor plan and the optimized pipelines would have been manual. Ah, life was so simple when Dennard scaling still worked. It does look from the die photo like there was a lot of rework on the right hand side with logic optimized, I
    – Tanj
    Aug 24 '19 at 19:37

Yes, Intel did make 486SX CPUs with no FPU on the die. You can see the difference in die shots, e.g. from this CPU-World.com thread: early 486SXs are nearly indistinguishable from 486DXs, but later 486SXs are simpler (the right-hand side has been reworked, and is missing the FPU which was in the lower-right-hand corner).

This is a 486DX:

486DX die shot

This is an early 486SX, with a disabled FPU on-die:

486SX die shot with disabled FPU

This is a later 486SX, with no FPU on-die:

486SX die shot with no FPU

  • 5
    What is hard to see directly from the pictures (no scale bar, not your fault!), is that the lower-most die (the 486SX with no FPU) is actually smaller than the top die. This is, of course, why they did that. Once yield was high enough on the 486DX units, and demand was still there for 486SX chips, you got more die per wafer if the die are smaller.
    – Jon Custer
    Aug 21 '19 at 16:12
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    Some other manufacturers produced equivalents to the 486SX under licence, and these also physically lacked the FPU. A relevant example was the 486SLC made by TI (and also sold by Cyrix), which was capable of reducing the clock speed to zero, unlike the Intel design which used dynamic logic. However it used the i386SX bus protocol and was therefore slower.
    – Chromatix
    Aug 21 '19 at 18:14
  • @Jon yup, the large uniform areas in the bottom half are supposed to be the same size in all three photos, so the bottom photo should be narrower. Aug 21 '19 at 20:57
  • It also would not surprise me if there was a process shrink in there somewhere that would decrease the die area even more (not a process node chang, just tweaking of the layout rules to allow higher density).
    – Jon Custer
    Aug 21 '19 at 21:07
  • @JonCuster I've edited the post to set a narrower width for the no-FPU-on-die image. (SO allows IMG tags with certain parameters that let me do this.) It doesn't come out perfectly in all situations and browsers, but should help get the idea across.
    – cjs
    Aug 22 '19 at 3:51

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