Wikipedia page for memory controller states that memory controllers are either part of the northbridge, or in more recent cases, integrated into the processor.

But AFAIK, neither IBM 5150 nor Altair 8800 had a northbridge. So, how did these computers access memory? Where was the memory controller for these machines?

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    The Altair 8800, or am I ignorant? – Tommy Apr 20 '18 at 14:54
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    One of the key issues is speed. Comment instead of an answer as I don't have enough specifics/time to research right now. RAM in the 1970s & 1980s was more or less directly linked to the CPU. Very little on-chip memory, if any, beyond the registers, so RAM had to keep up with CPU - if you pushed a CPU from 4.77 to 8 Mhz then your RAM better be able to keep up or the system will crash. Modern systems manage memory in hardware, including on-chip cache & preloading of memory in various ways. Direct RAM access (i.e., to addresses not cached or anticipated) is much slower than the full CPU speed. – manassehkatz Apr 20 '18 at 15:54
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    @manassehkatz - right, or looked at another way: there was no point in having a fancy memory controller architecture, because a stock CPU wasn't fast enough to need anything special when used with regular, commodity RAM. It wasn't until the 386 became common that CPUs started to be fast enough that the RAM systems of common PCs were struggling to keep up. – Jules Apr 21 '18 at 3:06

"Northbridge" is a rather modern and PC specific term and is used to denote the bridge chip that connects the CPU to fast peripherals such as PCI buses and memory and that (usually) contains a memory controller. So for machines that don't have a northbridge, the answer is "somewhere else".

The Altair 8088 can use either DRAM or SRAM boards. Each DRAM board has its own memory controller, and the SRAM boards conveniently don't need anything beyond some chip select logic (but SRAM is expensive). If there is more than one memory board installed, there will be several independent memory controllers in the system. This setup is quite common for modular, backplane based computers.

In the case of the 5150, there is no dedicated "memory controller" chip. There are just a bunch of simple 74xx chips hanging off the (only) CPU bus that generate the chip select signals for the memory, and the 8237 DMA controller and the 8253 timer that generate the refresh signals (amongst other things).

Less stingy designs used dedicated memory controller chips like the AM2964 or DP84322 which combine address multiplexer, refresh counter, row and column address logic etc. in a single chip.

Even back in the day, some CPUs such as the Z80 included memory refresh logic directly in the CPU to reduce chip count. Many modern CPUs include the memory controller directly in the CPU because it's faster. Examples for this are AMDs Athlon and Opteron, IBMs Power5, and Intels i5 and i7 CPUs.

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    The discrete (74LSxxx) logic approach was not only cheaper, it was almost always faster. I designed more than one memory system back in those days (Z80, 68000, and 68030) and found that the discrete logic could be tuned for better results than the general purpose controllers. Those chips were largely confined to larger systems (eg Multibus etc) where the bus overhead made counting wait states much less important. – Peter Camilleri Apr 20 '18 at 20:44

The memory controller is (theoretically) not an essential part of a computer system, but it's present on modern-day desktops because it provides very convenient mechanisms for security, multiprocessing and other things.

In the computers you mentioned, and in early microcomputers generally, the memory controller is not there because the CPU simply accesses the memory and I/O directly. In such systems, everything that needs to use the bus is connected to the bus, and there is a single bus connecting the CPU, the memory, I/O devices, etc.

Something that may be relevant is that DRAM needs a refresh signal, and a memory controller may provide this. Some CPUs, such as the Z80 which could be installed in the Altair, provides this signal. Otherwise, it may be generated by a simple electronic circuit.

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    In the specific case of the IBM 5150, memory refresh signals are generated by channel 0 of the DMA controller. – john_e Jul 29 '16 at 15:00

The actual CPU bus (which would be called the "frontside bus" on 686-era designs) on the 8086, 80386, 68000 and similar CPUs IS more or less a memory bus.

Typical peripheral chips (UARTs, floppy controllers, CRTCs) and the (in case of a PC compatible machine) ISA cards using them have a very similar electrical interface to a bunch of memory chips, and are talked to in roughly the same way.

The same applies to the BIOS/BASIC ROMs - they are memory, and they are on the CPU bus.

Some glue logic parts (bus buffers like the 74xx245, latches like the 74xx374, address decoders like the 74xx138) will be required to use that bus, but not a dedicated memory controller chip.

In that era, there was another kind of device sometimes called a "memory controller", which was actually a so called MMU (memory management unit). These provided virtual/swappable/remappable memory capability (IF your system design wanted it. The 5150 doesn't have one.) and WERE complex, additional chips, but they were integrated into CPUs relatively early (the 286 has one built-in, the 68000 and 8086/8088 do not).

There were also off-board DMA controllers, which are in effect another part that "controls memory". These were, for a long time, dedicated chips or integrated into the chipset.

  • Good point. Basically, the only thing you need for a memory controller in a system like the 5150 is a latch to store the address, a couple of buffers with either tristate or open collector outputs, and some delay lines that make sure the buffers are activated in the right sequence, in order to multiplex the wide address provided by the CPU into the row and column addresses expected by DRAM chips. – Jules Apr 21 '18 at 3:13
  • IIRC there are actually one or two delay lines on a 5150 board, would have to check the schematics about what they do... – rackandboneman Apr 21 '18 at 10:14

Wikipedia page for memory controller states that memory controllers are either part of the northbridge, or in more recent cases, integrated into the processor.

A 'Northbridge' is a specific PC term for one or more integrated support chips to handle all address based access(*1). They are not something neccersarry per se for any CPU, not even a x86 in a PC.

But AFAIK, neither IBM 5150 nor Altair 8088 had a northbridge. So, how did these computers access memory?

A CPU does not need a memory controller. It just puts out a memory access and waits for data to return (or being taken). CPUs produce all signals to access memory (*2). The issue is just the other way around: Certain memory needs a additional circuitry to be accessable to a CPU. DRAM for example is the most prominent player here, as it (may) need several additional functionality, usually not supplied by a CPU.

Functions needed (may) be:

  • Dynamic RAM does (*3) need multiplexed addressing. The non multiplexed address supplied by a CPU must be send thru a multiplexer before the RAM can decode it.

  • Dynamic RAM also (*3) needs refresh. Without they will loose their content quite fast. Some refresh circuit is needed to nurture the data. Usually thats some counter and a bunch of latches, as well as some ready/wait logic to keept the CPU from interfering.

  • Dynamic RAM offers (*3) an access feature called Page Mode that can speed up access time quite a lot when accessing data within a certain region (page). To make it work some page register and glue logic is used.

  • Dynamic RAM with page mode can be aranged in groups with having different pages opened in each goup - nowadays called ranks. Ofc this needs additional page registers and glue logic.

  • Todays dynamic RAMs even offer protocols to open several pages within a single RAM (rank), which again needs external hardware to handle it.

  • RAM content can be protected by using some parity scheme. To make it work a parity generator, compare logic and logic to issue a memory fault interrupt is needed.

All of these RAM features do need additional circuitry to offer/support these features/neccesarries. A CPU does not need to know about this at all, as it just puts out a memory request and waits for data.

So why isn't it integrated within the RAM chips?

Cost. It's all about volume and money. A bare RAM design can be used in many more systems than specialized ones. Also using the advanced features is always dependant on CPU specific issues. RAM manufacturers didn't want to build Motorola or Intel specific chips but targetet the market at whole.

Again, how was it done on the PC?

Where was the memory controller for these machines?

The original PC didn't use any of the advanced features mentioned above. Just address multiplexing and RAM refresh had to be done. The multiplexing was handled by a set of 74LS158 multiplexers, while RAM refresh was done by a cyclic inserted DMA request using DMA chanel 4 of the 8237 DMA controller, triggered by Timer 1 of the 8253 Programmable Interval Timer.

So these components formed what you might call a memory controller. Over the years the seperate IC got integrated into more complex system components - starting with Chips and Technologies NEAT chipset - leading to finally integrating them the into todays CPUs. On the way there more and more of the additional features got integrated.

So no Memory Controllers Before the NEAT chipset?

No. There were controllers. Already way before the PC. Integrating the required seperate IC into more complex one to simplifying DRAM usage was done early on. For the 8088 IBM could have used Intels fiting 8208 DRAM controller instead, handling everything about DRAM, but they did go for a cheaper solution.

*1 - Address Based Access - huh? Well, I had to find a way to describe access of data via a combination of address lines, daa lines and controll ines - something (next to) every CPU features. It's not just memory, as this also includes I/O addressig and alike.

*2 - Like the 8088 features (in Minimal Mode) with 20 address lines, 8 data lines, ALE, RD, WR and IO/M every thing that is needed to connect memory or other memory/IO-mapped devices. A colplete system can be done with as little as 4 chips - 8088, 8284, 8755 and 8155 (or 8185).

*3 - Here a bunch of adjectives like 'usually', 'originally' or 'mostly' may be inserted, as there are always special RAM versions available where such functions are already build in - ofc, these more complex/special purpose chips are more expensive and usually not found in PCs.

  • "A CPU does not need a memory controller. It just puts out a memory access and waits for data to return (or being taken)." -- assuming that the CPU uses a bus protocol that is designed at least roughly the same way as memory is. This isn't always the case, though, for instance AMD processors since the early 2000s have used HyperTransport to communicate with the outside world, which is actually much more like a networking protocol than a traditional memory type bus. – Jules Apr 21 '18 at 3:18
  • @Jules No, not realy. Well, yes, they (K9ff) offer HT, and it's used to connect multiple CPUs and Chippsets, but DRAM is hooked direct to an integrated memory controller. HT is only used when accessing memory of another CPU (NUMA). Access, DRAM or HT, is handled via a crossbar making it (almost) invisible to a programm. The crossbar is hooked to the CPU via a 'traditional' address/data bus. There is one crossbar complex available to feed all cores of a chip. The difference between K8 and K10 is that K10 has the L3 as common part of the crossbar (and cache is in line with access, not parallel). – Raffzahn Apr 21 '18 at 9:58

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