Wikipedia page for memory controller states that memory controllers are either part of the northbridge, or in more recent cases, integrated into the processor.
A 'Northbridge' is a specific PC term for one or more integrated support chips to handle all address based access(*1). They are not something neccersarry per se for any CPU, not even a x86 in a PC.
But AFAIK, neither IBM 5150 nor Altair 8088 had a northbridge. So, how did these computers access memory?
A CPU does not need a memory controller. It just puts out a memory access and waits for data to return (or being taken). CPUs produce all signals to access memory (*2). The issue is just the other way around: Certain memory needs a additional circuitry to be accessable to a CPU. DRAM for example is the most prominent player here, as it (may) need several additional functionality, usually not supplied by a CPU.
Functions needed (may) be:
Dynamic RAM does (*3) need multiplexed addressing. The non multiplexed address supplied by a CPU must be send thru a multiplexer before the RAM can decode it.
Dynamic RAM also (*3) needs refresh. Without they will loose their content quite fast. Some refresh circuit is needed to nurture the data. Usually thats some counter and a bunch of latches, as well as some ready/wait logic to keept the CPU from interfering.
Dynamic RAM offers (*3) an access feature called Page Mode that can speed up access time quite a lot when accessing data within a certain region (page). To make it work some page register and glue logic is used.
Dynamic RAM with page mode can be aranged in groups with having different pages opened in each goup - nowadays called ranks. Ofc this needs additional page registers and glue logic.
Todays dynamic RAMs even offer protocols to open several pages within a single RAM (rank), which again needs external hardware to handle it.
RAM content can be protected by using some parity scheme. To make it work a parity generator, compare logic and logic to issue a memory fault interrupt is needed.
All of these RAM features do need additional circuitry to offer/support these features/neccesarries. A CPU does not need to know about this at all, as it just puts out a memory request and waits for data.
So why isn't it integrated within the RAM chips?
Cost. It's all about volume and money. A bare RAM design can be used in many more systems than specialized ones. Also using the advanced features is always dependant on CPU specific issues. RAM manufacturers didn't want to build Motorola or Intel specific chips but targetet the market at whole.
Again, how was it done on the PC?
Where was the memory controller for these machines?
The original PC didn't use any of the advanced features mentioned above. Just address multiplexing and RAM refresh had to be done. The multiplexing was handled by a set of 74LS158 multiplexers, while RAM refresh was done by a cyclic inserted DMA request using DMA chanel 4 of the 8237 DMA controller, triggered by Timer 1 of the 8253 Programmable Interval Timer.
So these components formed what you might call a memory controller. Over the years the seperate IC got integrated into more complex system components - starting with Chips and Technologies NEAT chipset - leading to finally integrating them the into todays CPUs. On the way there more and more of the additional features got integrated.
So no Memory Controllers Before the NEAT chipset?
No. There were controllers. Already way before the PC. Integrating the required seperate IC into more complex one to simplifying DRAM usage was done early on. For the 8088 IBM could have used Intels fiting 8208 DRAM controller instead, handling everything about DRAM, but they did go for a cheaper solution.
*1 - Address Based Access - huh? Well, I had to find a way to describe access of data via a combination of address lines, daa lines and controll ines - something (next to) every CPU features. It's not just memory, as this also includes I/O addressig and alike.
*2 - Like the 8088 features (in Minimal Mode) with 20 address lines, 8 data lines, ALE, RD, WR and IO/M every thing that is needed to connect memory or other memory/IO-mapped devices. A colplete system can be done with as little as 4 chips - 8088, 8284, 8755 and 8155 (or 8185).
*3 - Here a bunch of adjectives like 'usually', 'originally' or 'mostly' may be inserted, as there are always special RAM versions available where such functions are already build in - ofc, these more complex/special purpose chips are more expensive and usually not found in PCs.