How did the Altair 8800 front panel load the program counter?

Question

My understanding is that when you toggle in an address on the Altair 8800 front panel switches and then press the EXAMINE switch, it loads the program counter with that address, or at any rate does something so that you can then press SINGLE STEP or RUN to start executing the instruction at that address.

How exactly does it load the program counter, given that there's no obvious way to tell the CPU to do this without excecuting instructions to do so? Does it actually put instructions on the bus and get the CPU to execute them? Or is there some other clever trick?

References to schematics are welcome; if you can provide additional information on exactly how the circuits work, that's even better.

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A Note on the Answers:

I've accepted 比尔盖子's answer because after (slowly) walking through it in conjunction with the full schematic page I understood just how the data bus was being manipulated, which is the level of detail I was personally looking for. (His schematic excerpts really helped to make sure I was focusing on the right parts for each step.) But if you just want a more general description, or want an overview before diving into the details, you may want to read the other answers before the accepted one.

Answer 1

Just about a week ago, I encountered the same question as I was thinking about the idea of building a front panel for my homebrew computer, but I didn't understand how could one "move" the CPU to execute code at an user-specified address without affecting other components such as the content inside the RAM, I even searched at RC.SE! And so, I decided to take a look at Altair 8800. As I'm a bit late for the question, I'll just post some details from page 25 of the schematics to show the additional information.

The circuitry was surprisingly simple and clever.

1. When the "Examine" button is pressed it generates a high pulse to 1CK below to activate a counter made from two 7473s. Also, at this point, there is no memory or I/O activity, the bus is free.

2. (a) On the first count, the processor is started, and a logical "1" is sent to four 7405 inverter gates, which are connected to data line D2, D3, D4, D5. Thus, they are pulled to ground and became hardwired logical "0". The 7405 is used, because it has open-collector outputs, it either pulls a line down, or doesn't touch the line at all, avoid the need of tristate outputs.

2. (b) On the other hand, the undriven pins D0, D1, D6, D7 are kept at logical "1", because the data lines have 4.7k ohm pull-up resistors.

2. (c) As a result, the opcode 11000011, generated from a completely hardwired circuit, is injected directly on the data bus. Also, the address bus is completely ignored - no matter what address the CPU wants to read from, it gets the ones and zeros we just injected, which is the opcode for JMP.

3. On the second count, another 8 gates of 7405 inverters are activated, correspond to the 8 toggle switches for address bits A0-A7. If a switch is toggled, it completes the circuit and allows our 7405 to pull the line to logical "0". Otherwise, the lines are untouched and kept at logical "1" by pull-up resistors. Thus, the CPU gets the next byte from the data bus, still injected by us, which is the low 8-bit part of the 16-bit address.

4. On the third count, another 8 gates of 7405 inverters are activated in the same way, this time, they correspond to the 8 toggle switches for address bits A8-A15.

5. Therefore, CPU gets the final byte we injected from the data bus. At this point, the CPU has fetched a complete instruction,

   JMP XXYYh

   where JMP is generated by our hardwired circuit, and XX and YY are derived from the toggle switches. Great, we have just modified the Program Counter without affecting anything else!

6. On the fourth count, the counter resets, which in turn pulls EXM line low, and causes PRDY to be low and stops the processor again.

Appendix I: How does Altair 8800 avoid bus conflicts?

Cautious readers would immediately notice a critical problem: The RAM is not disabled while we're injecting instructions to the data bus! It means, the RAM would also respond and start outputting data simultaneously, creating a bus contention.

How does Altair 8800 avoid this problem? First of all, it's important to notice that our code injection circuitry and the toggle switches from the front panel are not connected to the demultiplexed, buffered "normal" data bus, instead, it is connected directly to Intel 8080's bidirectional "raw" data bus, see page 24.

From this segment of the schematics, one can see that all the data from the CPU to the bus ("output") is buffered by a group of 8T97 tristate buffers, all the data from the bus to the CPU ("input") is buffered by another group. When the CPU needs to write data, the output buffer is enabled, driving the data from the CPU to the bus; when the CPU needs to read, the input buffer is enabled, driving the data from the bus to the CPU.

The key to our success is this part of the circuitry, which is connected to pin 1 of the 8T97 buffer, responsible for enabling/disabling the input buffer.

It will enable the input buffer and allow the data to flow towards the CPU, only if the following conditions are met (see page 4).

1. CPU needs to read data from the data bus (DBIN), or the CPU releases data bus due to DMA (HLDA)

2. The front panel is switched to Run (RUN) or Single Step (SS) mode.

3. The buffer is not explicitly disabled by the /SSW DSB signal from the front panel.

When the front panel is used for examining the memory, the RUN/STOP switch is flipped to STOP. As a result, the Condition (2) is unsatisfied, the input buffers are disabled, effectively isolating the CPU from all RAM and I/O ports, leaving only the pull-up resistors and our front panel. Therefore, the bus contention problem is avoided without disabling the RAM explicitly.

Meanwhile, the RAM is not disabled for a good reason: we need to inspect them. To do this, indicator lights are simply connected to the "normal" bus lines (DI_0-7).

The final conclusions:

• When we need to examine the RAM: Instead of driving the address bus and generate the proper RAM-access signals by ourselves, we simply exploit the existing Intel 8080 CPU to do it for free, by injecting a JMP instruction.

• When we need to capture the data from RAM: Instead of latching the data by ourselves, we simply disable the input buffers, inject the instructions from one side, and watch the bits coming out from RAM to the indicator lights at the other side.

• As a side-effect, this process also modifies current Program Counter of the CPU.

Using this simple circuit design and a minimum number of components, we hit three birds with one stone. This design is not without its limitation, which helped to explain the reason behind two oddities on the Altair 8800: (1) "EXAMINE" also modifies PC, (2) The indicator lights only shows input, not output.

The designers in Ed Roberts's company must have put great effort to reduce the cost and complexity of the Altair 8800 system.

Appendix II: What is /SSW DSB?

As you see, pulling the signal /SSW DSB to ground will disable the input buffers as well. Why don't we use this signal? What is it?

The Altair 8800 has a special input port, 0xFF, which is the current position of the sense switch. As I mentioned, toggle switches are connected directly to the raw, unbuffered 8080 data bus. If we want to read the input from the sense switch, the input buffer must be switched off. The /SSW DSB is used for this purpose.

Signal /SSW DSB is generated to switch off the input buffer, when...

1. The CPU needs to read data from the data bus (DBIN).

2. The source is an I/O port (SINP).

3. The address is 0xFF (255).

Answer 2

How exactly does it load the program counter, given that there's no obvious way to tell the CPU to do this without excecuting instructions to do so?

Seams like you know it already :))

Does it actually put instructions on the bus and get the CPU to execute them?

That's exactly what is done: Let the CPU jump to that address.

In case of 'EXAMINE' the front panel injects a jump to set the desired address. When presses, a JMP (opcode 11 000 011) is inserted, followed by the two address bytes and one cycle to halt the CPU again. All orchestrated by a little sequencer build from the two flip-flops of a 7473.

In case of 'EXAMINE NEXT', similar, a NOP (opcode 00 000 000) gets inserted to make the CPU advance to the next address.

'DEPOSIT' issues a single memory write cycle without having the CPU do anything, while 'DEPOSIT NEXT' does the same plus triggering the NOP execution of 'EXAMINE NEXT' after that.

(Looking at page 25 of this scan of the manual will show it to you in all detail)

Or is there some other clever trick?

Isn't already quite clever?

The basic trick is the same as with Sinclair's ZX80 Video access (which itself is an application of the 'Cheap Video' circuit) and others. Except operating in stop motion :))

Answer 3

The IMSAI 8080 front panel seems to be nearly identical to the Altair 8800 front panel.¹ I just stumbled across a 1999 document, IMSAI CPA Front Panel Control Board, that gives an excellent description of how this works:

Several CP-A function switches operate by providing the 8080 with an instruction, executing the instruction, and then stopping the processor on the next cycle. The open collector 7405's and support gating put these instructions on the 8080's bi-directional bus. The EXAMINE function uses a jump instruction (hex C3) followed by two bytes of the address selected on the front panel switches. This operation causes the processor to jump to the selected address and, then, the processor is stopped during the next cycle. When stopped, the processor was reading the selected byte from memory as if it were going to execute it. Therefore, the processor stops with the desired address displayed on the address bus and the contents of that address is displayed on the data bus. If the RUN switch is operated at this time, IMSAI 8080 CPA Front Panel the processor will continue to pull the selected byte from memory and execute it.

The EXAMINE NEXT and DEPOSIT NEXT switches use similar schemes and the NO-OP (hex 00 or octal 000) instruction to increment the address. Much of the remaining logic of the CP-A is used to sequence these commands to provide the desired functions. The RUN/STOP flip-flop line, the SINGLE STEP line, the EXAMINE line, and the EXAMINE NEXT-line are all input to an OR-gate controlling the X-READY line. (The X-READY line must be high for the processor to run its function is identical to the P-READY line used by the memory and I/O boards. The X-READY line is reserved for use of the front panel to avoid conflicts of two gates driving the same backplane line). During each of these functions, the processor is permitted to execute an instruction, and then is stopped in the next cycle in a manner similar to the RUN/STOP flip-flop cycle described earlier

For the SINGLE STEP function, a one-shot, triggered by the SINGLE-STEP switch, is used to produce a pulse and the trailing edge of that pulse is used to set a flip-flop, which controls the SINGLE STEP line. This permits the processor to execute the present instruction. [Actually, not the whole instruction but just one machine cycle of the current instruction. --cjs] The SINGLE STEP flip-flop is reset by the occurrence of the sync pulse on the following instruction [actually machine cycle --cjs], thus causing the SINGLE STEP level to be removed and the processor to stop on the following cycle.

The EXAMINE-NEXT flip-flop is similarly controlled by the leading edge of a pulse from a one-shot driven by either the DEPOSIT NEXT or EXAMINE NEXT switch. The output of the flip-flop is used both to put the NO-OP (hex 00 or octal 000) onto the bi-directional data bus, and also to provide the READY signal so that the processor will execute the instruction. It is reset by the sync pulse on the following cycle, thus stopping the processor again.

The document goes on to explain EXAMINE and DEPOSIT in similar detail, including the use of a gating to ensure that the MPU board is not trying to drive the data bus while the front panel is using it to write to memory.

Unrelated to this, the document also explains the EXT. CLR. (CLR on the Altair) switch, which sends a reset signal to everything but the processor, which I had been wondering about.

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¹ _{The Altair's interrupt acknowledge light, INT, is called INTA on the IMSAI. The WO light (write/output cycle) on the earlier Altair front panels was actually negative logic; this is correctly labeled W̅O̅ on the IMSAI. The PROT light and PROTECT/UNPROTECT switches don't exist on the IMSAI, but most Altair memory boards didn't support the protect feature anyway. The IMSAI adds RUN, WAIT and HOLD lights that don't exist on the Altair, as well as the PROGRAMMED OUTPUT lights displaying whatever was written to the latch on port FFh. All switches appear identical in both designation and operation. Much of the information in this note came from deramp5113's Altair 8800 Video #4 - Front Panel Status Lights and Video #5 - Interrupt Acknowledge Cycle.}