In short, 3 µm looks like it was the "standard" process size at the time, and it was available to Commodore before the chips were designed. Therefore it looks like using the larger 5 to 7 µm process nodes was a deliberate choice in designing these chips. But I can't seem to find a sound reason why.
What I know so far
As this case study from IEEE spectrum states, the VIC-II was designed for a 5 µm process, and the SID used a 7 µm process which occasionally dipped to 6 µm.
This doesn't make a lot of sense to me because by the time these chips were designed beginning in 1981, 5 µm and especially 7 µm processes were outdated: 3 µm was available and used in actual products (like the Intel 8085) no later than 1976. Some products in development were even using 1.5 µm already, such as the Intel 80286 and NEC's 64k RAM, which were released in the same year the Commodore 64 was released in 1982.
The obvious culprit would be if MOS/Commodore specifically didn't have 3 µm yet, but according to this question, they probably had 3.5 µm by 1980, over a year before design for the VIC-II and SID began in 1981.
In interviews, the chip designers have cited chip area as a notable limitation. In other words, there were solid engineering reasons to prefer working with a smaller process and working with a larger process anyways had a clear negative impact on the design process. So the larger process nodes must offer something fairly significant to justify such restrictions.
So why did they intentionally design these chips using a larger process node?
Possible (entirely speculative) reasons
These are some things I've thought about, but I have absolutely no basis for believing any of them are true. I'm hoping some else will know more and offer some actual insight.
- Was the older 5 to 7 µm somehow cheaper than the newer 3.5 µm?
- Was 3.5 µm manufacturing not mature enough to risk for the new design? (seems unlikely, but maybe)
- The newer 3.5 µm was HMOS-I instead of NMOS. Is that somehow significant?
- The VIC-II & SID were originally designed with the idea of being sold for use in other systems. This explains some design restrictions, like why the VIC-II couldn't assume DRAM is necessarily larger than 16 kB or faster than 2 MHz, even though the specific DRAM in the Commodore 64 was 64 kB and could in theory handle clocks faster than 2 MHz. I can't think of any sensible reason why larger nodes would help broader compatibility, but compatibility clearly influenced other quirky design decisions, so maybe there's a link somehow?
EDIT: Rephrased first summary for clarity, and also rephrased second and fourth paragraphs for clarity