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According to the C64 wiki, asserting G̅A̅M̅E̅ on the cartridge port (and not asserting E̅X̅R̅O̅M̅) of the C64 leaves three blocks of the C64 address space "unmapped": 28 KB @ $1000 (otherwise RAM), 8 KB @ $A000 (otherwise BASIC ROM or, in some modes, ROMH on the cartridge) and 4 KB @ $C000 (otherwise RAM).

Is it safe for the cartridge to respond to read and write requests to these areas? (Say, because the cartridge wanted to have I/O in that area or—for some reason I can't currently fathom—its own RAM.) I assume here that the cartridge would have its own address decoding to handle this, and that the hardware would be kept off the bus until software had set up the C64 memory map properly to unmap these areas before enabling the cartridge to respond to them.

I ask because I know that even when certain onboard devices (in this case, RAM) are not mapped in, they still respond to write requests. (I have verified that writing to KERNAL ROM will of course not change the ROM, but still write to the RAM at the same addresses.)

If this is possible, are there any cartridges out there that actually use this technique?

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asserting /GAME on the cartridge port of the C64 leaves three blocks of the C64 address space "unmapped"

No, at least not alone. /EXROM also needs to be high. Otherwise standard RAM/ROM configuration prevails.

Is it safe for the cartridge to respond to read and write requests to these areas?

Yes.

I assume here that the cartridge would have its own address decoding to handle this,

As usual, as there are no select lines beyond /ROMLOW and /ROMHIGH, selecting 8 KiB each at $8000/$E000.

and that the hardware would be kept off the bus until software had set up the C64 memory map properly to unmap these areas before enabling the cartridge to respond to them.

No, that's not necessary, as the mapping is done in hardware. With /EXROM=High; /GAME=Low all CPU side memory mapping (HIRAM, LORAM, CHAREN) is simply disabled. Attention to the CPU port signals is only required if the cartridge 'decides' to change the /EXROM;/GAME setting.

I ask because I know that even when certain onboard devices (in this case, RAM) are not mapped in, they still respond to write requests.

Yes, but that's not for 'certain' devices, only the RAM. Its handling and timing is entirely controlled by the 82S100 PLA. THe very same chip doing the EXROM/GAME decoding. So the effect is either on purpose or more plausible simply due not caring. It generates RAS/CAS signalling for each and every access, no matter what address is used (*1).

If this is possible, are there any cartridges out there that actually use this technique?

I bet some did.


*1 - That way, even the RAM behind the build in port at 0000/0001 gets writen each - also great for external (debugging) hardware to help follow up on it's state

  • So to clarify, the RAM chips' write enable () is asserted for every write cycle in the C64 regardless of what other devices are also enabled? Asserting just R̅A̅S̅ and C̅A̅S̅ is not enough for the RAM to do a write. – Curt J. Sampson Sep 20 at 14:58
  • @CurtJ.Sampson Right, WE is the signal indicating that a write is to be made. A RAS/CAS cycle only defines a read - with the extended CAS signal as well used for read enable. One issue with the C64 design is that OE is grounded. – Raffzahn Sep 20 at 18:36
  • Acutally, according to this answer writes to $0000 and $0001 do not write through to RAM. – Curt J. Sampson Sep 21 at 17:39

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