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I was taking a look at the logic diagram in the manual for the original IBM game port adapter card:

IBM game card schematic

In the upper-left corner of the schematic, there is the circuitry responsible for decoding the I/O address lines from the host system. As I read it, it's constructed from two discrete 74LS138[1] decoders cascaded in the following way:

  • U2 is reading address lines A4 - A9. It expects all lines to be low except for A9, which is expected to be high. If those conditions are met, the Y0 output is pulled low.
  • U1 is reading address lines A0 - A3, AEN, and the Y0 output from the previous decoder. It expects all lines to be low except for A0, which is expected to be high. If those conditions are met, the Y0 output is pulled low.
  • The Y0 output of U1 controls activation of the entire rest of the card, based on signals from either /IOW or /IOR.

74LS138 Truth Table

|           INPUTS           ||                 OUTPUTS               |
| G1 | G2A | G2B | C | B | A || Y0 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 |
| ---|-----|-----|---|---|---||----|----|----|----|----|----|----|----|
| X  | X   | H   | X | X | X || H  | H  | H  | H  | H  | H  | H  | H  |
| X  | H   | X   | X | X | X || H  | H  | H  | H  | H  | H  | H  | H  |
| L  | X   | X   | X | X | X || H  | H  | H  | H  | H  | H  | H  | H  |
| H  | L   | L   | L | L | L || L  | H  | H  | H  | H  | H  | H  | H  |
| H  | L   | L   | L | L | H || H  | L  | H  | H  | H  | H  | H  | H  |
| H  | L   | L   | L | H | L || H  | H  | L  | H  | H  | H  | H  | H  |
| H  | L   | L   | L | H | H || H  | H  | H  | L  | H  | H  | H  | H  |
| H  | L   | L   | H | L | L || H  | H  | H  | H  | L  | H  | H  | H  |
| H  | L   | L   | H | L | H || H  | H  | H  | H  | H  | L  | H  | H  |
| H  | L   | L   | H | H | L || H  | H  | H  | H  | H  | H  | L  | H  |
| H  | L   | L   | H | H | H || H  | H  | H  | H  | H  | H  | H  | L  |

Putting everything together, the card activates if A0 and A9 are high while everything else (including AEN) is low. That's 1000000001b, or 201h. And hey, the card responds to I/O address 201h.

Now the question: Nothing on the card verifies that address lines A10 - A19 are low when decoding the I/O address. If that's true, and the schematic doesn't omit anything that's actually on the board, that means the card would activate on any I/O operation on an address whose low 9 bits matched 201h, regardless of the high bits. (So, 601h, A01h, E01h...) Did that actually occur in practice on the real hardware?

Cursory tests in DOSBox do not show a game port on any of the alias addresses above 201h, but I take that with a grain of salt.

[1]: It's not clear in the scanned schematic, but it's super clear in a photo of the board: SN74LS138N

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  • DOSbox is just emulation so they might not implement the address mirroring... btw the therm in English is port aliases or Address mirroring ? I did not see the first one till now ... I am just curious.
    – Spektre
    Commented Sep 21, 2019 at 3:48
  • @Spektre I'm not sure if the term I used is formal or correct. "Aliasing" is a concept from signal processing that feels similar to the behavior I asked about.
    – smitelli
    Commented Sep 21, 2019 at 12:51
  • @Spektre: Having addresses "alias" each other is a thing in computer architecture, too, e.g. when you have the same physical page mapped at two different virtual addresses. (Handling this correctly is a challenge for virtually indexed and/or tagged caches; architects should design caches to avoid homonym and synonym problems, perhaps with help from the OS by doing page coloring. Definition/meaning of Aliasing? (CPU cache architectures) / Virtually indexed physically tagged cache Synonym) Commented Nov 1, 2022 at 21:52
  • @Spektre: In x86-16, with the A20 gate disabled or on a true 8086, addresses like FFFF:FFFE alias low addresses like 0000:FFEE, so that's another case where the term gets used. And yeah, in this case, with devices that only decode the low 10 bits, you could say that two port numbers alias each other if they're the same in their low 10 bits. Commented Nov 1, 2022 at 21:55

1 Answer 1

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The original IBM PC and AT designs allocated 10 bits for I/O addressing, and only decoded address lines A0-A9 for on-board I/O devices. However there was no physical limitation to 10 bits, so a card could use A10-A19 so long as it didn't clash with the aliases of 10 bits cards or motherboard devices.

So yes, the game-port card has aliases at 601h etc., but you are not supposed to use them.

Modern PCs have 16 bit I/O addressing and filter the 10 bit addresses so legacy devices don't clash with others using the full 16 bit I/O range. This may explain why DOSBox doesn't show any aliases.

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  • Still trying to figure out how things were wired. If a program did MOV DX,FFFFh then OUT DX, AX, would that light up everything in A0 - A15 or just A0 - A9?
    – smitelli
    Commented Sep 21, 2019 at 2:27
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    Yes, it would 'light up' everything, but there was nothing looking at A10-19 so what was on them was irrelevant. The entire (official) I/O address space was duplicated many times, but provided nothing tried to decode the upper address lines it didn't matter. There was no benefit (and potential danger) to accessing devices at their aliases so nobody did. Commented Sep 21, 2019 at 2:41
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    @smitelli, as BA (upvoted) says, the 8088/8086 CPU I/O instructions use a 16-bit I/O address but the IBM PC design only uses the lower 10 bits of this address. It's a rule imposed by the original designers that all hardware and software is expected to follow.
    – TonyM
    Commented Sep 21, 2019 at 16:41

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