I was taking a look at the logic diagram in the manual for the original IBM game port adapter card:
In the upper-left corner of the schematic, there is the circuitry responsible for decoding the I/O address lines from the host system. As I read it, it's constructed from two discrete 74LS138[1] decoders cascaded in the following way:
- U2 is reading address lines A4 - A9. It expects all lines to be low except for A9, which is expected to be high. If those conditions are met, the Y0 output is pulled low.
- U1 is reading address lines A0 - A3, AEN, and the Y0 output from the previous decoder. It expects all lines to be low except for A0, which is expected to be high. If those conditions are met, the Y0 output is pulled low.
- The Y0 output of U1 controls activation of the entire rest of the card, based on signals from either /IOW or /IOR.
74LS138 Truth Table
| INPUTS || OUTPUTS |
| G1 | G2A | G2B | C | B | A || Y0 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 |
| ---|-----|-----|---|---|---||----|----|----|----|----|----|----|----|
| X | X | H | X | X | X || H | H | H | H | H | H | H | H |
| X | H | X | X | X | X || H | H | H | H | H | H | H | H |
| L | X | X | X | X | X || H | H | H | H | H | H | H | H |
| H | L | L | L | L | L || L | H | H | H | H | H | H | H |
| H | L | L | L | L | H || H | L | H | H | H | H | H | H |
| H | L | L | L | H | L || H | H | L | H | H | H | H | H |
| H | L | L | L | H | H || H | H | H | L | H | H | H | H |
| H | L | L | H | L | L || H | H | H | H | L | H | H | H |
| H | L | L | H | L | H || H | H | H | H | H | L | H | H |
| H | L | L | H | H | L || H | H | H | H | H | H | L | H |
| H | L | L | H | H | H || H | H | H | H | H | H | H | L |
Putting everything together, the card activates if A0 and A9 are high while everything else (including AEN) is low. That's 1000000001b, or 201h. And hey, the card responds to I/O address 201h.
Now the question: Nothing on the card verifies that address lines A10 - A19 are low when decoding the I/O address. If that's true, and the schematic doesn't omit anything that's actually on the board, that means the card would activate on any I/O operation on an address whose low 9 bits matched 201h, regardless of the high bits. (So, 601h, A01h, E01h...) Did that actually occur in practice on the real hardware?
Cursory tests in DOSBox do not show a game port on any of the alias addresses above 201h, but I take that with a grain of salt.
[1]: It's not clear in the scanned schematic, but it's super clear in a photo of the board: SN74LS138N
port aliases
orAddress mirroring
? I did not see the first one till now ... I am just curious.FFFF:FFFE
alias low addresses like0000:FFEE
, so that's another case where the term gets used. And yeah, in this case, with devices that only decode the low 10 bits, you could say that two port numbers alias each other if they're the same in their low 10 bits.