There is simply no need for setting Overflow. The same is as well true for Negative/Sign and Zero. No operation will be influenced by any of them, it's only used to signal an overflow during
SBC (well, and
BIT for testing bit#6).
In fact, the question is rather, why there is a
CLV present, as there is no reason, within the boundaries of the instruction set, to set or clear V at all (*1). Any of the three
V changing instructions will always set/reset it without looking at the former state (*2). Looking at the various transfer instruction it seams rather that
TAY ist out of order.
The need to add
CLV becomes obvious when considering that hardware can set V via the SO (Set Overflow) input pin.
The combination of SO input and the
BVC instruction creates the shortest possible timing to react for an external signal. Having
BVC loop on itself will reduce reaction time to a maximum of 3 cycle.
L1 BVC L1
Way shorter than any IO test or interrupt handling. In fact, the overhead is zero (compared to more than 13 clocks with an interrupt (*3)) and all response time is reduced to 'instruction jitter' i.e. the time needed before either condition can be detected and the instruction stream is redirected. With an interrupt the actual instruction always needs to finish, which may take anywhere between 1 and 6 cycles. (*4)
Since this can only work as intended if V is cleared before entering the loop, software needs a way to do so. That's why
CLV got added.
V was choosen:
The reason why
V has been used is simply that of the non-modal flags (*5),
Z are changed with next to any data manipulating instruction, while
V is only influenced by
SBC. By using
V, it is still possible to write meaningful programs that check for an external events while doing other tasks, essentially allowing synchronous event detection with the least possible effort.
Any generic IO-Test would require at least a
BIT instruction (if the bit to test is #6 or #7) and a follow up branch, resulting in at least 5/6 cycles and 4 bytes used. If not placed that nice, it'll needs loading and testing a value, which not only needs more cycles and program bytes, but as well destroys a register as well, serious reducing usefulness. With SO and
BVS detection can be inserted as often as needed by spending just two bytes and two cycles (in case of not set) each.
Background: Other CPUs
While the V/SO combination is quite restricted and seams more like added on afterthought, having direct testable CPU pins was quite common. Basically two types were used:
In any variation the goal was to allow a few (usually 1..4) input pins to be checked with as least instructions and as fast as possible.
In addition some had as well similar fast output pins.
- Intel 8085 -
SIM instruction to read SID and control SOD
- Valvo/Signetics 2650 - Two bits (#6/7) in upper status register (PSU) with #6 controlling an output pin (Flag) and #7 reflecting the (Sense) input pin.
- Valvo/Signetics 2650 - As well as direkt I/O instructions (
REDD) for two implied addressed ports (called Command/Data).
- Fairchild F-8 - Had two 8 bit ports on chip (*6), operated by special short
- National SC/MP - Maxes the Flag-in-Status-Register concept with two input bits (Sense A/B) and 3 output (Flag 0/1/2)
- RCA/Intersil CDP1802 - Offering a single output (Q) set/reset by
REQ and four inputs (EF1/2/3/4). The Inputs are not visible in any status register (the 1802 doesn't have one) but direct testable by a separate set of branch instructions (
- General Instruments CP1600 - Maxing out the testable input lines to 16 by having a special branch instruction (
BEXT- Branch on EXTernal condition) which outputs a 4 bit address on EBCA0..4 and reads the addressed bit via EBCI.
*1 - Likewise for
*2 - Unlike the related Carry flag, which needs not only to be checked, but also cleared or set before doing an
*3 - 7 for the interrupt itself plus 6 for
RTI -being an interrupt it as well preservation of registers will usually be needed, weras done via
BVC (as wait or inline) will already have all registers set as they need to be and no need to restore.
*4 - Not 7, as an instruction only needs to finish when already started :)
*5 - Modal flags are such that change CPU operation, like the Decimal or Interrupt Disable
*6 - No, despite its odd style, it's not a microcontroller