It appears that A0 through A6 operate correctly, but A7 though A9 (I've not tested the rest of the upper bits) are only active on the clock edge.
Doesn't that exactly look like refresh cycles? :))
Basic Z80 bus behaviour, here especially the M1 cycle:
- Z80 timing is structured in Machine cycles (M-states).
- A machine cycle consists of several Clock cycles (T-states).
- The first M cycle of any operation is M1 (signalled as such on the /M1 pin).
- A M1 cycle is done whenever an opcode is read.
- The M1 cycle takes 4 clock cycles.
- The M1 cycle consists of two memory operations: Opcode access and refresh.
- During the first two clocks (T1, T2) of an M1 cycle the PC gets outputted on A0..A15 and the opcode gets fetched.
- A refresh is done during the next two cycles (T3, T4) of a M1 cycle.
- During a refresh the 8 bits of the refresh counter (
R register) get outputted on A0..A7(*1).
- Only the lower 7 bits of
R are a counter, bit 7 is not modified (*2).
- A8..A15 is not valid (*3).
- During M1 the
R register gets incremented by 1.
Implications for your setup
- A NOP features a single machine cycle.
- It is always a M1 cycle
- Your 'program' thus consists of only M1 cycles.
- It takes 4 clock cycles to execute.
- During the first two clock cycles the
PC gets outputted.
- During the next two clock cycles
R get outputted (*4).
R get incremented with each M1 cycle.
- After Reset
I) are zero.
PC increments modulo 65536.
R increments modulo 128.
You see the picture?
For the first 128 steps, the address outputed during opcode read (T1, T2) and refresh (T3, T4) is (seams to be) the same, after that,
R restarts, while
PC continues. If you had traced 1025 (*5) steps you may have noticed that sequence again - giving an even bigger headache :))
Do I have a bad CPU?
No, there is nothing wrong, your CPU works exactly like expected.
I guess, whoever did make the original design, didn't explain the finer details, as it works great within the given setup - that is, unless LED get attached to A7..A15.
P.S.: This question is so classic RTFM, one has to love it - that and the clear and complete description the OP provided, makes me want to give it +5 points :))
*1 - To be exact, only A0..A6 are validated by /RFSH
*2 - Bit 7 is (like all of
R) cleared after reset, but can be modified when
R is set via
*3 - Neither the 1976 nor the 1984 manual mention what happened on the upper 8 bits, but actual (2004) Z80 CPU User Manual states that
I gets outputted. This is consistent with the way the registers are organized, so it is save to assume the same behaviour for any Z80.
*4 - Plus
I on the upper 8 bits.
*5 - With 10 LED your setup injects a modulo 1024 behaviour as well.