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I just got a Z84C0020PEC and wired it up to test it, using this circuit:

enter image description here

Except that I've added LEDs to A0 through A9. It appears that A0 through A6 operate correctly, but A7 though A9 (I've not tested the rest of the upper bits) are only active on the clock edge. That is, those LEDs flash when they should be staying on. Is this normal behavior? Do I have a bad CPU?

  • OT - which vendor in China did you get the chip from, and how much current does it draw? – Bruce Abbott Oct 24 at 20:50
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    @Bruce: I purchased "Simple80 Z80 CPU/SIO Homebrew IC Kit" from seller hth-tech on eBay. How do you want the current draw measured?...Running NOP's?...Wait?...Halt?...No LED's? – Mike Oct 25 at 0:30
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    Thanks. No LEDS, running NOPs will be fine. Reason for asking is the last so-called CMOS Z80s I bought off eBay were NMOS chips that drew about 200mA, so I'm curious to know who might be selling real ones. BTW that refresh effect fooled me too at first. – Bruce Abbott Oct 25 at 1:32
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    @Bruce: As above circuit, no address LED's, but with one LED (w/1Kohm) on the clock and using two more NAND's (so the LED doesn't interfere with the clock). Measures a max of 2.5mA running NOP's. – Mike Oct 25 at 2:40
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    @Bruce: Oh, and I'm clocking it at about 2Hz (yes, two). – Mike Oct 25 at 2:48
40

It appears that A0 through A6 operate correctly, but A7 though A9 (I've not tested the rest of the upper bits) are only active on the clock edge.

Doesn't that exactly look like refresh cycles? :))

Basic Z80 bus behaviour, here especially the M1 cycle:

  • Z80 timing is structured in Machine cycles (M-states).
  • A machine cycle consists of several Clock cycles (T-states).
  • The first M cycle of any operation is M1 (signalled as such on the /M1 pin).
  • A M1 cycle is done whenever an opcode is read.
  • The M1 cycle takes 4 clock cycles.
  • The M1 cycle consists of two memory operations: Opcode access and refresh.
  • During the first two clocks (T1, T2) of an M1 cycle the PC gets outputted on A0..A15 and the opcode gets fetched.
  • A refresh is done during the next two cycles (T3,T4) of a M1 cycle.
  • During a refresh the 8 bits of the refresh counter (R register) get outputted on A0..A7(*1).
  • Only the lower 7 bits of R are a counter, bit 7 is not modified (*2).
  • A8..A15 is not valid (*3).
  • During M1 the R register gets incremented by 1.

Implications for your setup

  • A NOP features a single machine cycle.
  • It is always a M1 cycle
  • Your 'program' thus consists of only M1 cycles.
  • It takes 4 clock cycles to execute.
  • During the first two clock cycles the PC gets outputted.
  • During the next two clock cycles R get outputted (*4).
  • Both, PC and R get incremented with each M1 cycle.
  • After Reset PC and R (and I) are zero.
  • PC increments modulo 65536.
  • R increments modulo 128.

You see the picture?

For the first 128 steps, the address outputed during opcode read (T1, T2) and refresh (T3, T4) is (seams to be) the same, after that, R restarts, while PC continues. If you had traced 1025 (*5) steps you may have noticed that sequence again - giving an even bigger headache :))

Do I have a bad CPU?

No, there is nothing wrong, your CPU works exactly like expected.

I guess, whoever did make the original design, didn't explain the finer details, as it works great within the given setup - that is, unless LED get attached to A7..A15.


P.S.: This question is so classic RTFM, one has to love it - that and the clear and complete description the OP provided, makes me want to give it +5 points :))


*1 - To be exact, only A0..A6 are validated by /RFSH

*2 - Bit 7 is (like all of R) cleared after reset, but can be modified when R is set via LD I,A.

*3 - Neither the 1976 nor the 1984 manual mention what happened on the upper 8 bits, but actual (2004) Z80 CPU User Manual states that I gets outputted. This is consistent with the way the registers are organized, so it is save to assume the same behaviour for any Z80.

*4 - Plus I on the upper 8 bits.

*5 - With 10 LED your setup injects a modulo 1024 behaviour as well.

  • Thank you for your reply, Raffzahn. I'm going to spend more time going through it. I also recently got a copy of "Z80 Users Manual" that I need to read. The behavior was just so inconsistent to me that I assumed there was a problem (the CPU was purchased used, not new, from China). – Mike Oct 24 at 14:59
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    A typically minor comment from me, not affecting my +1 vote: having checked my recollection on A8...A15, per z80.info/zip/z80cpu_um.pdf on the page labelled 3 which is the 17th page of the PDF: "During refresh, the contents of the I Register are placed on the upper eight bits of the address bus." But I=0 is guaranteed after reset (EDIT: confirmed by page labelled 20; 34th in the PDF: "A CPU reset clears the I Register so that it is initialized to 0."). – Tommy Oct 24 at 21:21
  • @Tommy Ah ja, good addition. Above was written from memory, and I sliped.... thinking of it, I got to go thru this again, as I have a few more parts of by 1. – Raffzahn Oct 24 at 21:39
  • You answered with a question. – Pedro Lobito Oct 25 at 2:40
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    @Raffzahn: I suspect it's a reference to your opening with "Doesn't that exactly look like refresh cycles?" But there's nothing wrong with that, and there's a lot more to your answer than that. – Fred Larson Oct 25 at 14:36

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