Sun's SBus is particular for having virtual addressing and address translation even for device drivers.

Any other buss design which had this peculiarity ?

Check out Ben Catanzaro's book The SPARC technical papers.

This is an addition to the latest DMA questions

  • 2
    Doesn't any decent system with paged virtual memory require either (a) bus-address virtualization, or (b) device controllers that have their own scatter-gather mechanisms. Otherwise you're left with (c) I/O into physically-contiguous buffers with data copy into the user-space not-necessarily-contiguous buffers. Solution (a) seems like it's cheaper than (b) and more efficient than (c).
    – dave
    Nov 2, 2019 at 13:25
  • @another-dave Operating systems often have the ability to wire specific physical address ranges into the kernel address space. Option c is not necessarily inefficient. You can map the pages directly into user space.
    – JeremyP
    Nov 5, 2019 at 8:25
  • Sure, but that does not fit the conventional paradigm where the user code decides where it wants the data: read(file, buffer, length)
    – dave
    Nov 5, 2019 at 12:47

2 Answers 2


DEC PDP-11 and VAX systems using the Q-Bus had a 'Q-bus map' to map from the bus address space into the physical memory space. This is basically an MMU for devices. On an I/O request from a program, the driver and OS would allocate and initialize map registers, and pass the appropriate bus-virtual address to the device.

It's possible for a contiguous bus-virtual address to be non-contiguous in physical memory, which probably mattered on VAX but not on the -11 systems I programmed.

The Q-bus map is necessarily separate from the map used by running programs (PARs/PDRs in -11, page tables in VAX) because the program that requested the I/O is not necessarily current on the CPU by the time the I/O transfer happens.

See section 3.8.1 in this technical manual for an arbitrarily-chosen MicroVAX CPU. You'll note that the entire map is actually held in physical memory, with a 16-entry TLB to avoid memory accesses. That is, it's your basic (system-wide) page table arrangement.

Similar arrangements exist for Unibus machines, and in particular, the map is needed when there's more than 124 Kwords (18-bits-worth less the I/O page) of memory, since the Unibus is only 18 bits wide.


Nowadays there is such thing as IOMMU, when every device that needs to do DMA with system memory, receives essentially virtual address and the host converts that address with the help of IOMMU device, before actually going into physical memory.

Therefore, we can say that PCI-express have this feature as well, though the address is irrelevant to the bus, it is the target on that bus, who does really care of the address.

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