I am studying basic principles of instruction set architectures and am considering what it would take to not have any instruction decoding at all. I.e., all the control lines of the computer would be found directly in the bits of the instruction word?
As a corollary, then, every instruction execution would take exactly one cycle (perhaps with 2 or 3 phases within a cycle, but not several micro-instruction cycles).
I have seen one home-brewer with a relay computer talk about that idea, and it grew on me. But I wonder if it is even possible or if it is traded off against variable length instructions.
I have found that there are really 3 opposing forces:
- Instruction size constant one word vs. variable multiple words.
- Full word instruction operands for immediate values and absolute addresses vs. address segmentation scheme.
- Data vs. address bus same size, you can read an address in one memory fetch, vs. address bus bigger than data bus where you need to read an address in multiple memory accesses.
And these 3 are mutually opposing. You can't have full word instruction operands in a constant instruction, and certainly not if your data bus is smaller than your address bus. E.g., typical 8 bit computer with 16 bit address bus. So the 6502 had to be (1) variable word instructions, (2) full word immediate values, while (3) absolute address values need multiple memory fetches.
The PDP-8 for contrast had (1) constant word instruction sizes, (2) no way to have full word immediate values or addresses, requiring a segmentation scheme, but (3) data and address bus the same size, or rather, address bus is completely separate.
And to that I add now:
- Instruction decoding mapping instruction word to control line states vs. instructions that have their control line immediately in their bits.
- Single (or 2-3 phase) vs. variable (multi) step micro-coding.
I know there is the entire RISC vs. CISC debate, but even a RISC processor will have multiple execution cycles for an instruction.
I wonder, was there ever a computer in use that needed no instruction decoding, i.e., where the control lines were immediately the bits of the instruction word?
This would only be possible in wider than 8 bit computers. I think the PDP-8 had a little bit of that, but still not quite. At least a pretty substantial hard wired instruction decoding gate network was there to interpret the bits of the the different instruction groups.
If you ave a 32 bit word size, then it could be possible to fit all the control lines into a single word. But still, I find that some of the control lines might have to be repeated to be used in different phases For example, now that I need a full 24 or 32 bit instruction word just for the control lines, I have to load any operands in additional fetches from the instruction pointer, then to go through indirect addressing I will need another fetch from data memory to be interpreted as an address for yet another fetch.
From your experience with odd stuff developed in the past, do you have examples for some of the less conventional ideas I brought up here?
UPDATE: I received a lot of feedback asking to define my terms better. I will try this here without changing my above text. So let's do a glossary:
Control Line: any logic line that controls a logic device, e.g., register output enable, register load, register asynchronous clear, counter increment, counter reset, counter decrement, memory write-enable, tri-state buffer output-enable, bus-transceiver direction, ALU function selection lines, etc. Usually there are dozens of these control lines all over a CPU and the point of instruction decoding is to set the state of these control lines based on the current instruction and other status lines (e.g., flags for the conditional branches, etc.)
Instruction Decoding: an instruction word is loaded into the instruction register, and that plus various status lines, and finally a micro-instruction counter will be the input of a state-control table. Input is the state lines and output is the control lines.
When I say "no decoding" in this context means that there is no need for such a state-control table, because the instruction word is comprised plainly of the bits of the control lines, but especially the number of microinstruction cycles is 1 or constant, not variable. I.e., every instruction takes the same number of cycles, without wasting any cycles either.
Cycle - a clock cycle, consisting of at least 2 phases, and 2 instantaneous moments. They are: rising edge (instantaneous moment), high state of clock (phase), falling edge (instantaneous moment), low state of clock.
Phase - given that any square wave clock signal has these 2 phases (high, and low) and their rising and falling edge moments, many processors require derivative signals. Sometimes called phi-2 or phi' (prime), etc. These are obviously necessary to subdivide a single clock cycle into multiple sub-steps in which different things happen.
An example for different things happening in the phases and moments of a normal square wave clock: rising edge: registers clock in the current state of the data bus or internal data bus, synchronous counters step at the rising edge. Falling edge: that's where a memory address latch may hold the address lines on a shared address/data bus so that in the low phase of the clock signal the data from memory appears on the bus while the address is held in the latch.
Microinstruction Cycle: when instructions are executed in multiple micro-instruction steps, for example:
- IR = *IP // load instruction from instruction pointer
- DP = *IP // load absolute address into data pointer
- DP = *DP + Y // resolve indirect address adding the Y index
- AC = AC + *DP + C // add with carry data from memory to accumulator register
Stuff like that.
What's decoding anyway? There has also been discussions about whether deriving some states from others is decoding or not? And whether register addresses have to have one line per register. I would say no. Register addresses may be a multi-bit binary number, and the register may decode that with a comparator to derive their line signal if the comparator find its address on the control line bus. In a more monolithic design, a 3-to-8 line decoder would also be "allowed" as it is not state dependent but only changes the "representation" of the register address from a binary number to a single line. Likewise, simple gating is "permitted". Just not complex state-control-transition tables.
RISC is the thing: By now I have studied more about RISC processors and it is clear to me now that RISC processors allow doing exactly that. With this approach, each instruction takes one cycle, and instead of short instruction words and micro-coding, we have long instruction words and no micro coding. I can see how it is possible to have 2 cycles per instruction one instruction fetch and one instruction execution.
Loading from absolute address would require two instructions, not two cycles of one instruction.
- load absolute address as an immediate value into data pointer
- read memory from data pointer.
Two instructions, each requiring 2 cycles: load the instruction, then load the data. Interesting that thinking this way there isn't even absolute addressing modes any more. Only immediate or implicit.
And in that model, indeed there are no "instructions" but only registers output to or loaded from the various busses and enabling certain transformation steps along the data path (inversion, sum, and, etc.)