In 6502 Assembly, we can use
INY to increase the value stored in X and Y. They can be decreased with
DEY. However, it seems that there are no such instructions for A, like
DEA. There is however an instruction to increment and decrement the content of an address (
DEC). But why are there no instructions like that for A? Does this have a reason? Or am I missing something? I know that you could just use
sbc but I'm still wondering.
In 6502 Assembly, we can use
The designers figured that you'd use X and Y for looping, indexing etc, and use A for adding and subtracting, shifts etc. So they saw a need for
INY, but didn't see a enough of a need for an instruction to increment or decrement the accumulator.
That's also the reason why X and Y cannot participate in many ALU operations, like adds, shifts, and whatever.
(Later, with the 65C02, the instruction you are talking about was added, and variously called
INC A or
If one writes opcodes in binary, using the format III-AAA-gg (with "III" generally being "Instruction", "AAA" being "Address mode", and "gg" as "general instruction group"), most instructions of the form III-AAA-01 or III-AA0-10 process addresses the same way using the address mode specified by AAA. The latter group of instructions are read-modify-write except that 10I-AAA-xx are LD_/ST_, with the registers selected by xx (in particular, 10I-AAA-10 are LDX/STX). The exception is that address mode 010, which would normally be immediate (e.g. ORA #imm is 000-010-01), becomes "accumulator" addressing for read-modify write instructions of the 0II-010-10 form. The increment and decrement instructions have the form 11I-AA0-10, which doesn't match that pattern.
The opcode map is a bit goofy in the areas which would match the general III-AAA-10 and 10I-AAA-xx patterns, but aren't used for read-modify-write or LD_/ST_ instructions. I would guess that instructions like "TXA" and "TAX", which are placed where "STX #imm" and "LDX #imm" would go, are placed at those spots to exploit the fact that instructions of the form 100-AAA-1x place X on the internal bus, and 101-AAA-1x loads X from the internal bus. I'm not sure when chronologically it was decided that various instructions would be supported, but supporting accumulator mode with INC and DEC would have required some extra circuitry, and would also require relocating DEX (which uses the opcode that would have fit the patterns of 110-AAA-10 for "decrement something" and 1x0-AAA-1x for "put something into X").
Incidentally, one thing that made chip designs of the 1970s and 1980s very different from those of today was that chips had only three layers that could carry current and signals, and any place the bottom two layers crossed would form a transistor. As a consequence, one needed to be very mindful of which signals would be sent to what part of a chip, or else a chip would spend more area on routing wires than on transistors. Today's fabrication processes generally support at least five layers, and many support far more than that, which allows much more routing flexibility.