I have been surprised at how little use eighties computers made of fast page mode access to RAM. (A notable exception being the Sinclair Spectrum, which used it to get the necessary bandwidth to video memory.) The Amiga, for example, used 41256 RAM chips of 150-ns speed grade, and performed a random access every 280 ns, but those chips are capable of better; even the older 4164s can do a pair of accesses in fast page mode in less than half a microsecond. The Archimedes widened the data bus to 32 bits, but a road not taken would've been to keep the data bus at 16 bits and use fast page mode to transfer a 32-bit word, or even a pair of such words. So I'm trying to figure out exactly what was the potential of the available chips.

Given the 41256 RAM chips of 150-ns speed grade, that were readily and cheaply available in the mid-to-late eighties, just how long would it take to read four consecutive words, the second, third and fourth in fast page mode?

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    A trivia aside: the Atari Lynx is another product of the '80s with a heavy reliance on paged mode. It even has a paged-mode predictor for its 6502, observing the opcode as it is fetched and consulting an instruction-length lookup table to get the required foreknowledge of whether following instruction bytes might be obtainable with paged mode accesses. I mean, it's not a computer, but it's highly computer-esque being a frame buffer and blitter rather than tiles and sprites, sitting between the Amiga and the 3DO in the Mical/Needle family. Design probably started c.1986.
    – Tommy
    Dec 26, 2019 at 16:40
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    ARM/Archimedes was also optimised for fast page mode DRAM. The rather "complex" instructions for a RISC (shifts, predications) was optimised to fit in page mode DRAM access time on computers without cache.
    – Grabul
    Dec 26, 2019 at 17:04
  • @TEMLIB Oh, how did that work? Was it a case of: each subsequent instruction would be fetched in fast page mode unless you happened to branch outside the previous page?
    – rwallace
    Dec 26, 2019 at 18:27

1 Answer 1


The speed rating of asynchronous DRAM devices is usually (as in this case), the "RAS access time" or tRAC. This is the minimum guaranteed time for data to appear at the output after /RAS is provided with the row address, noting that this process also requires /CAS to be provided with the column address at some intermediate time. The speed at which you can cycle RAS, and therefore perform consecutive random accesses, is tRC which is always longer than tRAC.

Referring to a Samsung datasheet for the 41256 family, I see that it has a "nybble mode" specifically for fast multi-cycle word loads, distinct from the "page mode". In the 150ns speed grade, tRC is 260ns (so nicely compatible with the Amiga's access cycle), while tNC for consecutive nybble-mode accesses is 75ns.

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    So if I understand correctly, the relevant datasheet is pdf1.alldatasheet.com/datasheet-pdf/view/37259/SAMSUNG/… and the numeric answer is 260 + 3x75 = 485 ns. Thanks!
    – rwallace
    Dec 26, 2019 at 16:51
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    That would seem like it would have been possible for a relatively modest amount of extra hardware in the Amiga's chipset to have greatly increased the amount of memory bandwidth available, even if the only thing that was done was to replace every four consecutive data fetches for each bit plane with a quad data fetch and three "non-fetches". The display chip would need an extra ~256 bits worth of buffering, but that's a fairly modest amount compared with everything else the chip contains.
    – supercat
    Jun 29, 2020 at 2:43

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