Because it needs the least chip count and thus makes it the cheapest. It's a Sinclair.
The Sinclair ZX80 used a Z80A running at 3.25 MHz. But this chip was rated for 4 MHz. Why was it run below rated speed?
And the chip would have run for sure at more than 4 MHz. A computer design isn't about what a chip is rated, but what it's for.
why not run the master clock at 8 MHz? The CPU and video generation were linked, but that just means a higher frequency would produce a higher horizontal resolution,
Sure, but clocking it at 8 MHz wouldn't have generated any gain for its designer, but acted against their goals. It's not about a single frequency, but, like any design, about finding a sweet spot between various goals. While there are many possible combinations, the absolute imperative for the ZX80 was to be cheap.
Speed was of no concern at all. There were other successful home computers with way lower clock speeds than 3.25 MHz (*1).
Main lever to lower cost is the number of gates. For the ZX80/81 a combination of line length, character per row, and pixels per character defined a sweet spot for hardware needed. By using parts of the CPU with as little external logic as possible to handle video generation, these add up to what resolution is to be used. For Details see below.
Atari 800 where the color burst frequency was an external reference standard that had to be taken into account.
The colour burst frequency is irrelevant for the workings of the Atari. It's the same with the ZX80. Using a single clock source for several issues keeps cost down and a colour burst frequency is needed anyway.
How it works
Since we're talking about TV, all we need to look at is a single line - and the way the hardware is used to generate it. So, let's take a first look at how a line is generated:
- At the beginning of a line the refresh counter is cleared (*2).
- Each character to be displayed is read from RAM like an instruction.
- The lower 6 bits are used to load a bit image from ROM during the refresh cycle (T3/T4).
- The value read is outputted via a shift register as 8 pixels at double the CPU clock
- The CPU gets fed a NOP instead.
- A single byte NOP instruction takes 4 clocks.
- Each single byte instruction contains one refresh cycle
- The refresh counter is incremented during each refresh cycle by one
- When the refresh counter reaches 32 it spills over to bit 6
- Bit 6 of the refresh counter issues an interrupt ending line generation.
So the CPU timing for the visible part of a line consists of 32 characters each handled in 4 CPU clocks each or 128 clocks in total.
- These 128 clocks need to happen within the visible part.
- The (maximum) visible part of a line is ~52 µs.
- It's safe to leave at least 10% on each side to make sure it's well within any TV, including rather misaligned ones (*3).
- As a result some ~40 µs is what line data should take (*4).
This means to deliver this, the CPU clock cycle should take 40 µs / 128 = 0,3125 µs or 3.2 MHz. 3.25 looks close, doesn't it?
What to do
Using the same hardware
One way to increase resolution would be outputting more characters per line (*5). Without adding more hardware, the next higher number per line would be 64, by taping bit 7 of the refresh counter. Now, while a TV in theory could handle this fine (*6), it would need doubling the clock frequency to 6.4 MHz. The CPU may in fact still go along, but ROM and RAM most definitely not. So, even with widening the used time, which would generate other issues in line timing, it's not really possible to get it much below 5.5 MHz (*7).
With the modulator used, the display would be hard to distinguish from static noise.
Modifying the hardware
Of course it is always possible to throw more hardware at the problem. So for example another gate to combine two bits of the refresh counter to detect line end. This would allow line length of 34, 36, 40 or 48 characters per line. By keeping the 40 µs limit, this results in clock frequencies of 3.4, 2.6, 4.0 or 4.8 MHz.
So yes, it would work as you imagine, 40 characters and 4 MHz, but it means an additional AND gate would be needed - since there is no unused one on the ZX80 board, this means a whole chip to be added. Not very Sinclair like.
*1 - For example the KC85 using a Z80 at 1,75 MHz or PMD 85 with an 8080 at 2 MHz
*2 - That's why the refresh counter can not be used for RAM refresh.
*3 - Aka text safe area.
*4 - AFAIR the real ZX80 uses ~37 µs, but as you'll see, 40 will give nice numbers allowing to do the math without a calculator.
*5 - Somewhat frivolous on a computer with just 1 KiB.
*6 - Assuming a good quality signal transmission.
*7 - Like using 46 µs of the line will result in 46 µs/256=0,18 µs or 5.55 MHz