4

I've read about the Z80 interrupt priority daisy chain and it hasn't answered my question.

When using interrupt mode 2, the Z80 needs to form a 16-bit address for an interrupt service routine. The most significant 8 address bits come from the I register and bits 1-7 come from the interrupting device.

So I'm assuming to get those bits from the interrupting device the Z80 needs to execute an IN A,(*) instruction (or other input instruction)?

When it executes that IN instruction, what gets put on the address bus for bits A0-A7? The interrupt enable daisy chain by itself doesn't seem sufficient to select the correct interrupting IO device, especially if address bits are used for chip enable logic.

If each IO device in the interrupt priority daisy chain has its own address, then the CPU can only fetch a vector from one of them at a time anyways, regardless of the priority of any particular device in the daisy chain. If the CPU doesn't put a valid address on the address bus, none of those devices would be selected anyways via the chip enable address bits.

For some reason, I can't find this specific point addressed in any of the Zilog documents. Does anybody know?

  • From this document zilog.com/… on pages 11 (description) and 12 (timing diagram) – Peter Smith Dec 30 '19 at 12:33
  • In the ZX Spectrum case, the normal value is the default data BUS value, 0xFF unless a device changes it. But the Z80 does not do an IN A, xxxx per se, it just uses the value that is in the data bus. – Rui F Ribeiro Dec 30 '19 at 12:38
7

So I'm assuming to get those bits from the interrupting device the Z80 needs to execute an IN A,(*) instruction (or other input instruction)?

[I assume the IN instruction mentioned is just meant as a place holder for an internal way to fetch the vector]

There is a special bus transaction to fetch the vector, the Interrupt Response Cycle, as shown here from the 2004 CPU Manual:

enter image description here

This cycle is marked by being an M1 cycle (/M1 asserted) but with IO-Request (/IORQ) asserted instead of Memory-Request (/MREQ). This happens during two additional cycles between T2 and T3 of the Interrupt Response (*1).

During this condition the interrupting device has to put out the desired vector number on D0..7.

When it executes that IN instruction, what gets put on the address bus for bits A0-A7?

Nothing, as there is no 'real' I/O addressing (*2). The combination of /M1 and /IORQ does the 'addressing'.

The interrupt enable daisy chain by itself doesn't seem sufficient to select the correct interrupting IO device, especially if address bits are used for chip enable logic.

Or course it can. After all, it's the whole purpose of the chain to determinate who is allowed to interrupt. A device issuing an interrupt 'knows' that it did so as it was pulling /INT without any higher priorized device disabling it. So when the Interrupt Response comes around, it can put its vector on the bus.

For some reason, I can't find this specific point addressed in any of the Zilog documents.

Please see:


*1 - While the documentation calls them wait states (Tw), they are in fact a different kind of T state i'd like ti call Ti. Regular wait states extend the T2 signalling without any other action, effectively halting the CPU. In contrast, the signalling changes during the first Ti state as /IORQ gets assigned.

*2 - To be correct, there is still the address of the instruction that would have been executed on A0..15. An arbitrary value with no meaning for I/O.

| improve this answer | |
  • 1
    Raffzahn, thanks for the detailed answer. As I thought about this more last night it occurred to me that IORQ and M1 could be used for the chip select logic. With that piece of the puzzle in place the daisy chain makes a lot more sense. It's just inconvenient in my case since I already soldered the boards together and now I need to rework them to accommodate IORQ and M1. Oh well. Thanks! – Dane Beck Dec 30 '19 at 20:00
7

No it does not execute any separate instruction to fetch the interrupt vector, but the CPU generates a special interrupt acknowledge bus cycle and during this cycle the interrupting device places the interrupt vector on data bus. That is then combined with I register to use it as an address from where to fetch the address to jump to.

| improve this answer | |

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.