I've read about the Z80 interrupt priority daisy chain and it hasn't answered my question.
When using interrupt mode 2, the Z80 needs to form a 16-bit address for an interrupt service routine. The most significant 8 address bits come from the I register and bits 1-7 come from the interrupting device.
So I'm assuming to get those bits from the interrupting device the Z80 needs to execute an IN A,(*) instruction (or other input instruction)?
When it executes that IN instruction, what gets put on the address bus for bits A0-A7? The interrupt enable daisy chain by itself doesn't seem sufficient to select the correct interrupting IO device, especially if address bits are used for chip enable logic.
If each IO device in the interrupt priority daisy chain has its own address, then the CPU can only fetch a vector from one of them at a time anyways, regardless of the priority of any particular device in the daisy chain. If the CPU doesn't put a valid address on the address bus, none of those devices would be selected anyways via the chip enable address bits.
For some reason, I can't find this specific point addressed in any of the Zilog documents. Does anybody know?