Looking at the pinout of e.g. the 8088, it multiplexes the data lines onto eight of the address lines; presumably the designers judged that being able to squeeze the chip into a 40-pin package, would save more total system cost than the extra logic required in the memory system.
Was there also a potential slowdown due to having to use the same pin for two different signals one after the other, instead of having separate pins? Or is it irrelevant because address has to come before data anyway?
Not that it would matter in the specific case of the 8088, which didn't drive the memory bus all that fast anyway, but I'm wondering if it would have been a limiting factor on a chip that did try to max out the memory bandwidth, e.g. using fast page mode where possible, and if so, whether 'we might need to make a cost-reduced version that multiplexes address and data lines' might have been one consideration to explain why pre-ARM CPUs did not max out the memory bandwidth (a surprising state of affairs in my opinion; memory bandwidth was a scarce resource, why leave some of it unused?).