Just to expand a bit, a cheap address decoder might not take all the address bits and decode them. For a 8 bit processor a simple address decoding scheme might use a 74LS138 to decode the high address bits (A15..A13) into 8K chunks of memory.
An alternative might be to use the high bit (A15) as an enable signal (connected to E1 on the 138) and wired to the CE pin on a 32K ram chip, allowing decoding of the top 32K into 4K chunks by wiring address pins A14..A12 to the 138 with 32K of ram from $0000-$8000.
Finally as a super cheap decode mechanism (used in various Sinclair computers for IO mapped devices) it's possible to use the address bus pins directly as chip enables i.e. 11110111 ($f7) where the single low bit selects which device. This allows 8 partially decoded devices without needing any decoding logic (although the spectrum only uses $fe so all IO ports on additional hardware need to be odd). This tended to be used more on processors with a separate IO space, otherwise using the rest of memory gets to be seriously complicated (particularly with DRAMs and refresh logic).