[Please see answers to this related question as well]

The NES Picture Processing Unit has eight memory-mapped registers to the CPU in registers $2000 to $2007. The are incompletely decoded, so they are mirrored every 8 bytes from register $2008 to $3FFF.

What does it mean that the memory is "incompletely decoded?" What is the purpose of nametable mirroring in the PPU?

  • 3
    Does this answer your question? What is the purpose of mirrored memory regions in NES's CPU memory map? Commented Sep 15, 2021 at 10:30
  • We sure shouldn't be closing two questions as duplicates of each other. Commented Sep 15, 2021 at 14:27
  • @OmarL No, that would be the worst possible solution. Bith are less than perfect, but tackle the issue from different angles, so people coming from either may find it useful. Lets crosslink them.
    – Raffzahn
    Commented Sep 15, 2021 at 14:42
  • @Raffzahn a cross-linked duplicate means that nobody is allowed to answer either one! Commented Sep 20, 2021 at 12:27
  • @user253751 Err, no, it's cross linked, but not duplicate, so one could answer either - or both
    – Raffzahn
    Commented Sep 20, 2021 at 13:41

3 Answers 3


Just to expand a bit, a cheap address decoder might not take all the address bits and decode them. For a 8 bit processor a simple address decoding scheme might use a 74LS138 to decode the high address bits (A15..A13) into 8K chunks of memory.

An alternative might be to use the high bit (A15) as an enable signal (connected to E1 on the 138) and wired to the CE pin on a 32K ram chip, allowing decoding of the top 32K into 4K chunks by wiring address pins A14..A12 to the 138 with 32K of ram from $0000-$8000.

Finally as a super cheap decode mechanism (used in various Sinclair computers for IO mapped devices) it's possible to use the address bus pins directly as chip enables i.e. 11110111 ($f7) where the single low bit selects which device. This allows 8 partially decoded devices without needing any decoding logic (although the spectrum only uses $fe so all IO ports on additional hardware need to be odd). This tended to be used more on processors with a separate IO space, otherwise using the rest of memory gets to be seriously complicated (particularly with DRAMs and refresh logic).

  • Petty observation: per the official documentation — zilog.com/docs/z80/um0080.pdf * — the z80's IN and OUT instructions provide fully deterministic, programmer-set values on all 16 address lines. So using those lines directly as chip enables allows 16 partially decoded devices rather than 8. (* "The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. The contents of Register B are placed on the top half (A8 through A15) of the address bus at this time.")
    – Tommy
    Commented May 4, 2017 at 14:05
  • True (and a good point) but the 8 bit instructions out (n),A and in A,(n) put the accumulator on the high lines of the address bus which does mean you need to use the out (c),r in r,(c) forms exclusively for a 16 bit address space (might be worth it if you're doing super cheap IO decode).
    – PeterI
    Commented May 4, 2017 at 14:23

"Incomplete decoding" means that the address decoder only pays attention to a few of the address lines: the high bits indicating the PPU chip and the three low bits selecting a register on that chip.

The purpose of doing this is to simplify things: by ignoring most of the address lines, the PPU chip needs fewer pins, while a three-bit address decoder is a much simpler circuit than a 16-bit decoder.


In modern parlance, we would refer to the registers being aliased every 8 bytes. As the other answers have identified, its something which costs logic resources to avoid.

Reasons to spend the gates and avoid aliasing would come down to considerations like reducing the validation space, which might be more important for security or safety critical applications (retro designs were simpler, and with more significant hardware cost).

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