According to Gordon Bell, the 6800 was based on the PDP-11. According to Chuck Peddle, it was a PDP-8.
Can anyone with knowledge of the PDP's pass judgement?
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Most sources say it was based on PDP-11.
Here are citations from the book "Early Home Computers", summarizing the similarities and the differences:
Unlike the PDP-11, 6502 and 8080, the 6800 was big-endian, as was the IBM 360 (...)
Unlike the PDP-11 and 6502, but like the 8080, the 6800 used borrow carry (...)
Unlike the 8080 and especially the PDP-8, but like the PDP-11, the 6800 had no special-purpose I/O instructions (...)
(...) the zero-page is similar to the zero-page mode of the PDP-8 (...)
The instruction set mnemonics owe a great deal to the PDP-11 (...)
Unlike the 8080 and the 6502, the 6800 had a complete set of branch instructions, basically identical to those provided on the PDP-11, for comparing both signed and unsigned quantities (...)
(available online in the Google Archive, page 875)
In spirit it's both, thus eventually neither.
Features of the 6800 can be put in line with many CPUs of that time - from PDP-8 and -11 all the way to TI's 990 or even IBM's /360 - but none will put it decisively into being based on either. In fact, many of the arguments that can be used to put the 6800 into PDP-8/-11 heritage can as well be applied to the 8080 - except, there is a quite clear lineage form the Datapoint 2200 to 8080 (and ultimately x86). It started before the PDP-11 and not really being anywhere like the PDP-8 - whose main feature is being a 12-bit CPU. So most of these similarities are rather due to the fact that these are obvious solutions than of a certain heritage.
As said, the similarities can at best be attributed to the designers being exposed to either DEC machine before, and thus seeing it through that preposition.
I wonder if there isn't a minor mistake in the CPU being discussed in one of those.
It's very easy to see the 68K as nearly a direct descendant of the PDP-11. The 68K has separate data and address registers, but programming it is mostly quite similar to programming a PDP-11.
I'd say the 6800 is (much) closer to a PDP-8. If memory serves, the 6800 has two accumulators and an index register (and PC and stack pointer). My recollection of the PDP-8 isn't quite as clear, but I think it had one accumulator, an index register, a "memory transfer register" (and a PC, but no stack pointer). So, both use an accumulator for most instructions, use a dedicated register for indirect transfers to/from memory, and so on.
On the other hand, it seems to me like it takes some thought to see the similarity between the PDP-8 and the 6800, where the similarity between the 68K and the PDP-11 always struck me as almost exceedingly obvious.
In overall feel, the MC6800 is clearly more like a PDP-11 than a PDP-8.
Like many machines of the 1950s and '60s, from the IBM 701 to DEC's
PDP-10, the PDP-8 was a word-oriented machine. Addresses pointed
only to full words, loads and stores were always of a full word¹, and
every instruction was exactly one word in size, with any operands
(such as an address) also contained in that same word. A major
consequence of this design is that the PDP-8 cannot directly address
its entire address space: the address field in an instruction word is
only 7 bits long, so address operands point either to an address in
the lowest 128 bytes of memory (if the addtional
Z bit in the word
is clear) or to an address the current page determined by the top 5
bits of the program counter.²
By contrast, the PDP-11 and MC6800 were byte-oriented machines, with 16-bit words being subdivided into two individually addressed eight-bit bytes which are often accessed as separate units of data, rather than as a whole word. Though the PDP-11 used word-length instructions and the MC6800 used byte-length instructions, in both cases at least some operands were separate words/bytes after the instruction word/byte, rather than always in the instruction word. Being able to use two-byte address operands after the instruction word/byte allowed both the -11 and the 6800 to access any byte in the address space from any instruction.
This division into bytes introduced two concepts that don't exist on word-oriented machines. Endianness refered to whether the lower byte of a word in memory was the most-significant (big-endian) or least-significant (little-endian) byte of an address. Alignment referred to whether or not a word was allowed to start on an odd address in certain cases. Word-oriented machines had no need for either of these concepts since a word was not divisible into smaller units.
Other similararities between the MC6800 and the PDP-11, and differences from the PDP-8, included the following:
The 6800 and -11 both used a stack, the head of which was pointed to by a register, for storing data and the return address of a subroutine. This made subroutines automatically reentrant (so long as the programmer stored all local data on the stack). The PDP-8 jump-to-subroutine instruction stored the return address in the first word of the subroutine itself, which necessitated special handling if the subroutine might be called again before it returned.
The 6800 and the -11 had no dedicated I/O instructions, instead having peripherals that monitored the memory addresses being accessed and responded appropriately when an address assigned to them was accessed. PDP-8 peripherals added new instructions to the instruction set.
The 6800 and the -11 had multiple registers available and operations
could be performed with only registers as operands. (For example the
ABA instruction would add the contents of the
B register to
A register, leaving the result in
A.) The PDP-8 had only a
single user-accessible register,
AC, besides the program counter,
and so all operations using more than one data value had to take the
second value from memory.
¹Some word-oriented machines did have facilities for sub-word access,
such as the "byte" instructions of the PDP-10, but the PDP-8 did not,
with arguably the exception of the
BSW instruction, present only in
the 8/e and later models, that swapped the two 6-bit "bytes" in a
²This was not the case, however, with many other word-oriented machines, which had longer words capable of holding a full address.
I say the 6800 is not like a PDP-11 in any useful way. It does not have general registers and it does not have addressing modes as a separate construction from the registers used by the mode. For example, the PDP-11 'indexed' mode is X(Rn), for n = 0 to 7; the case of n = 7 (the PC) gets you PC-relative addressing. By contrast the 6800 has only 1 register that is used for indexed mode.
Gordon Bell agrees with me (or rather, I with him!) in what makes the PDP-11 special:
The basic design decision which sets the PDP-11 apart was based on the observation that by using truly general registers and by suitable addressing mechanisms it was possible to consider the machine as a zero-address (stack), one-address (general register), or two-address (memory-to-memory) computer. Thus, it is possible to use whichever addressing scheme, or mixture of schemes, is most appropriate.
The 6800 appears to me to be more of a throwback to earlier designs (presumably to fit the silicon processes of the day) -- separate accumulator, index register, stack pointer. The PC is not an explicit component of operand evaluation; it's only implicitly involved in address modes that need further bytes from the instruction stream.
Where I think some of the confusion might have arisen, is that Peddle said:
A small instruction set, great addressing, was the model for the 11 that came under the Carnegie Mellon study, and we did the same thing.
So, he took some ideas from the set of ideas that went into the PDP-11. That does not mean that the 6800 is like a PDP-11 in any way really expressed in the ISA, just that the PDP-11 provided some inspiration or guidance.
My candidates for what ideas were taken:
the desirability of memory-access instructions being able to address all of memory
the desirability of indexed mode (constant displacement in instruction stream plus contents of index register)
the desirability of indirect addressing
These are all under the heading of "great addressing". The small instruction set observation is the realization that you don't need a huge instruction set, and allows you to make the tradeoff between using more bits for addressing-related use (e.g., address mode) and using them for more opcode bits.