It's doable if you have a lot of time, decent electronics skills, and some good test kit to figure out how the VIC video chip and the 6510 share the address and data bus. If I remember correctly, the 6510 reads/writes in one part of the clock cycle, and the VIC chip reads in the other part.
I know this because in 1990 a friend and I made a 4Mhz accelerator board for my Commodore 64 using many of the principles laid out in other answers. We used 2x32kb static RAM chips, a 4MHz 6502 derivative (can't remember which now, but it's still sitting in my parent's attic), and about 4-5 PAL chips to control all the logic.
We removed the 6510, plugged in the board we built to where the 6510 used to sit, and spliced a wire to the video clock (16MHz, which itself is divided by 16 to provide the CPU clock), which was then divided by 4. On every read cycle, the 4Mhz capable 6502 would directly read from the static RAM, and on every write cycle (the circuitry to synchronize clock cycles was very tricky) the 6502 would write to the static RAM AND the main board using the 1MHz clock (whether the RAM there, or special registers, whatever). Essentially, it was what we call today a cache.
It worked.... sort of. We could see programs running at about 3.5x regular speed for maybe a couple of minutes, but we could also see the screen filling up with random characters, indicating that something was corrupting memory. Inevitably, the programs crashed. We think that the VIC chip was somehow attempting read cycles that weren't quite synchronized with our clock cycles, but couldn't find a logic analyzer fast enough to figure out what was happening.
I still think this approach could work if you have modern test equipment, but it's months and months of work.