Many ICs generate such clock phases internally from a single-phase input, for example AY-3-8910: see clock divider in the central top position.
Such two-phase clock usually feeds alternating latches as to simulate the flip-flop behaviour, or is used when it is handy to break one-cycle design into two steps, each latched during its clock phase is active.
However, 6809 requires rather strange two-phase clock (see here, page 3, that consists of two square waves shifted by 90 degree. Actually, MC6809 generates those phases internally from x4 XTAL, but MC6809E, lacking XTAL generator, requires such phases as the input, so it could be thought as the internal requirement.
In what ways such shifted two-phase clocks are used inside the 6809? Are there any other designs with similar clock requirements? Are there any papers introducing this type of clocking?