Why did MC6809(E) require two-phase clock consisting of two square waves shifted by 90°?

Question

Usually when talking about two-phase clocks in early CPUs, one means this type of clock, that consists of two non-overlapped pulses. Examples are MC6800 clock (page 3) or i8080 clock (page 6).

Many ICs generate such clock phases internally from a single-phase input, for example AY-3-8910: see clock divider in the central top position.

Such two-phase clock usually feeds alternating latches as to simulate the flip-flop behaviour, or is used when it is handy to break one-cycle design into two steps, each latched during its clock phase is active.

However, 6809 requires rather strange two-phase clock (see here, page 3, that consists of two square waves shifted by 90 degree. Actually, MC6809 generates those phases internally from x4 XTAL, but MC6809E, lacking XTAL generator, requires such phases as the input, so it could be thought as the internal requirement.

In what ways such shifted two-phase clocks are used inside the 6809? Are there any other designs with similar clock requirements? Are there any papers introducing this type of clocking?

Answer 1

E is used for memory selection in a similar way as 6502 do (or 6800 phi2). Q should be used as a signal "data stable" (due to "The MC6809 Cookbook"). Let me quote:

Addresses from the MPU will be valid with the leading edge of Q. Data is latched on the falling edge of E.

It is called the "quadrature clock" and it is used sometimes in other systems too.

Below the line: The 8080 CPU uses a two-phase clock too, with more specific needs. The support IC 8224 generates the two-phase clock from a single time signal by division by 9. The first clock pulse has been active for 2/9 of the cycle, the other pulse is active for 5/9 of the cycle. (See the description of operation)

Answer 2

The skew between min and max propagation delays was a lot larger in old multi-micron NMOS processes (an understatement). The digital rise and fall times could be quite asymmetric. This made transistor sizing to prevent both setup and hold timing violations more difficult. Arithmetic combinations of a two phase (or more) or quadrature clocks allow creating non-overlapping logic or clocking pulses that are far more immune to these timing skew race conditions.

In NMOS precharge-evaluate logic methodology, one could also use the 1st quadrature quarter phase for precharge and that last half or 3/4 phase for evaluate logic, allowing more time for logic operations after the precharge.