tl;dr - I see the world divided into 'indirection indicated by dedicated field in instruction and (sometimes) in indirect words as well' versus 'indirection is a property of certain opcodes'. No 'indirection indicated by bit in address'. I think dedicated-field is more common.
I don't think there were many computers where indirection was indicated by a bit in the actual address. Some of the confusion may be more due to words used in the description rather than in the actual computer operation.
Most of my assembly-level experience has been with computers where indirection is a field in the instruction (and to a lesser extent, where chained indirection is supported, by a field in the indirect word).
Perhaps I have a big-machine (anything that can host a timesharing system) bias; perhaps early micros tended to specific instructions. I can't comment on that.
The case where there are distinct opcodes for indirection is obvious enough; I merely think it's not particularly common in the sort of machines I am used to. I don't discuss it further.
Machines with a separate field indicating indirection
Indirection is indicated by a separate field (not part of the opcode, not part of the address field). That is, it's the same MOVE or LOAD opcode regardless of whether there is indirection; in contrast to having a specific LOAD-INDIRECT opcode.
It may be useful to consider two subcases: single-level indirection and multi-level indirection, the latter being where the indirect word itself can call for another indirection.
Single level of indirection
If the indirection is not considered to be part of the opcode then it is a separate field in the instruction.
For the PDP-11, there are "mode" fields (potentially two, for operations with source and destination addresses), some values of which indicate "indirect" modes.
The VAX follows the PDP-11 model, except that some operations have more than two operands, but there's still a mode value as part of each operand specifier.
It seems unlikely that anyone would call this model "indirect flag in address".
Multiple levels of indirection
The initial indirection is again indicated by a field in the instruction word. The processor then fetches an indirect word which in the machines I am familiar with tends to have a similar format to the original instruction -- for example if the computer supports indirection and indexing, then the indirect word will also have an indirection indicator and an indexing indication (flag or register number).
For the PDP-10, there is an "indirect bit" in the instruction word and an "indirect bit" in the indirect word. The instruction and indirect words also indicate indexing by having a non-zero value in the "index register" field.
The SDS940 (which I have not programmed) is similar to the PDP-10. The instruction word contains an indirect flag and an index flag, considered as distinct from the address. Any indirect word also contains these flags. Indirection proceeds to arbitrary depth.
It may be considered a matter of opinion whether the indirect and index-reg fields are "part of" or "separate from" the address field. Since it is natural to consider them as separate in the actual instruction word, and since the indirect word follows the same overall format as the instruction word, the indirect/index fields are also best considered as separate in the indirect word.
Opinion on the above
In general, and even for computers I haven't programmed (but don't have them in mind's cache right now) this seems "standard" to me - to have a field or fields in the instruction that says how to form the effective address, but separate from the opcode and the address (displacement, whatever it is locally called).
I view this as clean design. It seems similar to having "use a modifier register (index register) in address calculation" not be implicit in the opcode but explicitly appearing in a separate field in the instruction word. Or even which register to use as source/destination, in a machine with register/memory instructions.
Machines quoted in the question
I have now read the Wikipedia page on the HP 2100. Based on that, I would describe the HP 2100 operation as follows:
An initial indirection is indicated by a field in the instruction (bit 15), which is not described (by the wiki page) as part of the address in bits 0-9; it is a distinct flag.
Optionally, a second indirection can be requested by setting bit 15 in the indirect word. And so on to any degree.
This is analogous in some way to the way the PDP-10 handles chained indirect. If bit 13 is set in the instruction, then it's indirect mode. If bit 13 is set in the indirect word (the one fetched from the effective address in the instruction) then it's another indirection.
For the HP 2100 case (a machine I am not familiar with), I would prefer to regard the indirect bit, bit 15, as a separate flag rather than part of the address. I have two reasons for this: (1) it's a separate flag in the instruction, not even contiguous with the address, so symmetry says it's a separate flag in the indirect word, (2) if bit 15 is set in the indirect word, then bits 0-14 are used as the address from which the next indirect word is fetched - i.e., bit 15 is not part of the address.
Even if it turns out I'm only quibbling about terminology, note that "bit in the address" as used in the HP 2100 is only a consideration for CPUs that have a multi-level indirect capability. Anecdotally, I think that's falling out of favour in mainstream processors.
(But the alternative is still not only "separate instructions for direct/indirect cases")
This user manual (which I assume to be authoritative) describes the instruction format as having an 'indirect' bit.
The format of relative addressing instruction is:
Byte 0 Byte 1
o: operation code
i: indirect addressing flag
a: relative displacement
and further, under the heading 'Indirect Addressing':
Indirect addresses are 15-bit addresses stored right justified in two
contiguous bytes of memory. As such, an indirect address may specify
any location in addressable memory (0-32767). The high order bit of
the two-byte indirect address is not used by the processor.
So I see nothing that would cause me to describe this as an indirection flag in an address. The flag is a separate field in the instruction, not part of the address and not implicit in the opcode.