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I am curently studying NES architecture to create a NES emulator. While looking up the NES motherboard schematics (https://console5.com/wiki/Nintendo_NES-001), some of the chips usage are not clear to me:

  • U2: 74LS373
  • U3: 74LS139
  • U7, U8: 74368
  • U9: 74HCU04
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    These are standard 74-series, TTL logic chips. For a useful answer, it might be helpful if you could be more specific about what you want to know. – Raffzahn Jan 23 at 1:33
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    Data sheets can be found just by typing the chip identifiers into Google (I tried and succeeded). – another-dave Jan 23 at 3:40
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    @another-dave Actually, an easier way to find the data sheets is to use Wikipedia's list of 7400 series integrated circuits, which provides brief descriptions of all of them and direct links to data sheets. – cjs Jan 23 at 4:33
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    74x373 is a register, x139 a decoder and x04 six inverters. – Uwe Jan 23 at 16:05
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    I looked into the data sheets, but it is easier to understand them in context, hence my question – Filipe Rodrigues Jan 23 at 18:38
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You may also find useful this other schematic, which I find easier to read, though some of the design details differ. It's from the NesDev wiki which is a fount of useful technical information about older Nintendo consoles.

All of the chips you mention are low-level interface logic, and probably not important for your emulation. You'll need to do the same things that those chips help to do, but almost certainly in different ways.

The 74LS373 is an 8-bit latch. When the ALE ("address latch enable") line of the PPU is high, the latch reads the data from AD0-7 and passes it through to A0-7 on the RAM chip. When ALE goes low it "freezes" the data on its outputs and ignores any changes to its inputs, basically "capturing" the low 8 bits of the address being sent to the RAM.

This is necessary because the AD0-7 outputs from the PPU are connected not only to A0-A7 of the RAM (though the latch), but also D0-7 of the RAM. (This multiplexing saves pins.) This is very hard to see due to blurred text on the schematic you linked, but much more clear in the one I linked above. So here's what a read cycle looks like:

  1. The PPU deasserts R̅D̅, generates an address on AD0-7 and asserts ALE.
  2. Because R̅D̅ is not asserted, the RAM disables its D0-7 I/O pins so that they will have no effect on the bus. Because ALE is asserted, the '373 reads its input pins and passes the address on AD0-7 through to the A0-7 pins on the RAM.
  3. The PPU deasserts ALE. This causes the '347 to start ignoring its inputs, and thus any data on AD0-7, and maintain the old value on its outputs, holding the address on RAM pins A0-7.
  4. The PPU asserts R̅D̅, enabling the RAM data outputs D0-7, and it can now read those data on pins AD0-7.

The 74LS139 is a decoder used for address decoding. Basically, it's a pair of units that take a two bit binary number as input to the A and B pins, and drive low one of Y0, Y1, Y2 or Y3 depending on what the input number is. (Or it may leave all of the outputs high if the chip is not selected.) Here's the function table ( is the select pin, which must be low to enable output):

    G̅  A  B      Y0 Y1 Y2 Y3
    0  0  0   →   0  1  1  1
    0  1  0   →   1  0  1  1
    0  0  1   →   1  1  0  1
    0  1  1   →   1  1  1  0
    1  x  x   →   1  1  1  1

In this particular case it's generating the enable signal for U1, the 2K static RAM. The inputs to the first half are the clock (φ2) and A15; if these are 1 and 0 respectively, Y1 goes low. (The clock is used here because the address and data for the memory are valid only when it's high.) Y1 in turn enables the second two-bit decoder, which takes A14 and A13 as inputs; if both are low then its Y0 output goes low, and that enables the RAM.

The effect of this is that accessing any address between $8000 and $AFFF will enable the RAM.

The 74368 is an inverting tri-state buffer, which has three functions that can be used alone or in combination: 1) inverting the signal going through it (changing low to high and high to low), 2) buffering signals so that something on the other side is driven with enough power, and 3) connecting or disconnecting whatever's on the other side of the buffer.

In this case these are used to connect shift registers in the gamepads to the data bus based on signals from the INP0 and INP1 pins, which are asserted when you read the ports $4016 and $4017.

The 74HCU04 is just a package of six unbuffered inverters, changing low to high and vice versa. This is not represented as a single chip on the schematic; the individual inverters are the triangles with small circles at the point that you see in various places on the schematic.

Most of these are used at various places where they simply want to invert a signal, but this particular form of 7404 can also be used as an amplifier, and it's used as such in the audio output circuit.

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    There's a significant difference in 74*HCU*04 inverters from quoted 74ls04 ones: HCUs are single-stage CMOS ones and thus could be used as analog amplifiers, for example in crystal oscillators or audio processing (both options are in NES). – lvd Jan 23 at 14:37
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    @lvd Thanks for pointing that out! Looking more closely, it appears to me that, though most of the inverters are used as standard digital inverters (where a 74LS04 would be fine), one is used as part of the audio circuit as an amplifier. I've linked to a data sheet that better describes the 'HCU04 and updated my description. – cjs Jan 23 at 15:52
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    I think you mean ports $4016 and $401*7*. – Mike Jan 23 at 15:58
  • Thank you - the schematics you linked and your post helped me understand partially the role of 74LS373. However, it is still not clear to me why does NES needs an "address latch". Is this related to retrocomputing.stackexchange.com/questions/2238/… ? – Filipe Rodrigues Jan 23 at 18:49
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    @Filipe No, it's not related to that other question at all; those are completely different latches. I was working out the '373 logic only from the schematic you provided, and due to blurred text I couldn't see that AD0-7 are actually connected to the address and data pins of the RAM. Re-examining this on the alternative schematic I found made this clear, and I've updated and expanded my answer to explain the need for the latch. Let me know if it's still not clear. – cjs Jan 24 at 2:41

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